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Thomas Edison ; 1889
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| Number | Title | Issue Date |
| 5243637 | Apparatus and method for assuring stable clock generator during oscillator start-up A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycle... | 09/07/1993 |
| 5128944 | Apparatus and method for providing notification of bit-cell failure in a redundant-bit-cell memory An erasable, programmable ROM (10) with three redundant bit-cell arrays (10A, 10B, 10C) includes an error-flagging circuit (30) that detects bit-cell failures and provides notification of each such failure. The error-flagging circuit (30) includes a plura... | 07/07/1992 |
| 5034624 | Apparatus and method for assuring stable clock generator during oscillator start-up A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycle... | 07/23/1991 |
| 4855623 | Output buffer having programmable drive current The specification discloses output buffer circuitry (10) for providing selected output driving characteristics. A plurality of input terminals (13, 24 and 30) receive control and data signals. A plurality of interconnected driver transistors (20, 28, 36 a... | 08/08/1989 |
| 4731553 | CMOS output buffer having improved noise characteristics A CMOS output buffer circuit which as improved noise characteristics is disclosed. The circuit has two stages, one having relatively fast response time for causing the output node to make a quick logic transition, and the other stage for providing steady-... | 03/15/1988 |
