Inventor: Douglas W. Stout

Address: Milton, VT
No. of patents: 37
Last patent issue date: 09/06/2011

Number	Title	Issue Date
8015526	Static timing slacks analysis and modification A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is perf...	09/06/2011
7821053	Tunable capacitor Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconduct...	10/26/2010
7619398	Programmable on-chip sense line Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When...	11/17/2009
7579897	Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first an...	08/25/2009
7475366	Integrated circuit design closure method for selective voltage binning Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an integrated circuit design into smaller successive intervals corresponding to a...	01/06/2009
7474124	Electronic circuit for maintaining and controlling data bus state The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-stat...	01/06/2009
7454305	Method and apparatus for storing circuit calibration information A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the re...	11/18/2008
7404163	Static timing slacks analysis and modification A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is perf...	07/22/2008
7348657	Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. ...	03/25/2008
7307467	Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at le...	12/11/2007
7266789	Method and apparatus of optimizing the IO collar of a peripheral image An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO collar...	09/04/2007
7222248	Method of switching voltage islands in integrated circuits when a grid voltage at a reference location is within a specified range An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (suc...	05/22/2007
7194707	Method and apparatus for depopulating peripheral input/output cells Chip area corresponding to unnecessary I/O cell sites is recovered and made usable for additional core cells and power connections by grouping I/O cells into I/O kernels of contiguous I/O cells having power connections independent of other I/O kernels and depopulati...	03/20/2007
7142991	Voltage dependent parameter analysis A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a p...	11/28/2006
7138701	Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. ...	11/21/2006
7107469	Power down processing islands A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a me...	09/12/2006
7088131	System and method for power gating Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection ...	08/08/2006
6927614	High performance state saving circuit A state saving circuit includes a state saving latch powered by an un-interruptible power supply, and a cut-off control device powered by the un-interruptible power supply that selectively connects the state saving latch to a pair of latch nodes based upon a control...	08/09/2005
6891207	Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. A control network can be used to control the bias...	05/10/2005
6883152	Voltage island chip implementation A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention ou...	04/19/2005
6825711	Power reduction by stage in integrated circuit An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this wa...	11/30/2004
6820240	Voltage island chip implementation A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention ou...	11/16/2004
6779163	Voltage island design planning A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage isl...	08/17/2004
6725439	Method of automated design and checking for ESD robustness A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wire...	04/20/2004
6667648	Voltage island communications circuits An integrated circuit comprising a first circuit powered by a first power supply. The first circuit sends a first signal referenced to the voltage of the first power supply to a second circuit powered by a second power supply. The second circuit receives ...	12/23/2003
6577178	Transient gate tunneling current control A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxide...	06/10/2003
6545521	Low skew, power sequence independent CMOS receiver device The present invention provides a receiver device having multiple voltage supplies that allows the output stage of the receiver device to go to a safe state whenever its voltage is disconnected or powered-down, independent of any of its normal control circ...	04/08/2003
6493257	CMOS state saving latch A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off co...	12/10/2002
6362653	High voltage tolerant receivers A high voltage tolerant receiver that matches a voltage drop across an NFET pass-gate at the input to the receiver with a voltage drop across a semiconductor device, formatted as a diode, and connected between an input stage and an input stage voltage sup...	03/26/2002
6292343	ASIC book to provide ESD protection on an integrated circuit An ASIC book comprising a gate-array format of ESD components is provided. A customized, optimized and tuned ESD network can be constructed from the ASIC book. Novel ESD circuitry having inter-rail ESD circuitry and single-rail ESD circuitry can be constr...	09/18/2001
6262873	Method for providing ESD protection for an integrated circuit A method for automatically generating a custom ESD network for an integrated circuit is provided. When a user provides chip size and chip capacitance for the integrated circuit, components for the customized ESD network are automatically selected based on...	07/17/2001
6157530	Method and apparatus for providing ESD protection A novel ESD protection circuit for multiple power supplies, having both inventive inter-rail ESD circuitry and inventive single-rail ESD circuitry. The inter-rail ESD circuitry is scaleable and comprises one or more diode strings for interconnecting a pai...	12/05/2000
6140846	Driver circuit configured for use with receiver A driver circuit has an input terminal at which a first signal having a first voltage swing is applied, and an output terminal at which: (i) a second signal having a second voltage swing is provided to external circuitry, and (ii) a third signal having a ...	10/31/2000
6087881	Integrated circuit dual level shift predrive circuit A dual stage voltage level predrive circuit for an integrated circuit chip including two level shifter stages in series. The voltage level shifting circuit uses single dielectric layer devices and three bias supply circuits each providing a different DC b...	07/11/2000
5151619	CMOS off chip driver circuit A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor and an N-channel pull down transistor serially arranged between a first voltage source having a supply voltage of a given magnitude and ground with the common point b...	09/29/1992
5134311	Self-adjusting impedance matching driver A self-adjusting impedance matching driver for a digital circuit. The driver has both a pull-up gate to VDD and a pull-down gate to ground. An array of gates is provided in parallel with each of the pull-up gate and the pull-down gate, with any one or mor...	07/28/1992
5127008	Integrated circuit driver inhibit control test method A method and apparatus for designing very large scale integrated circuit devices, most particularly level sensitive scan design (LSSD) devices, by inclusion of a plurality of distributed delay lines originating at input terminals of the device, and contro...	06/30/1992

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Inventor: Douglas W. Stout