Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Number | Title | Issue Date |
| 8368180 | Scribe line metal structure A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. ... | 02/05/2013 |
| 8361842 | Embedded wafer-level bonding approaches A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric... | 01/29/2013 |
| 8361895 | Ultra-shallow junctions using atomic-layer doping A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing... | 01/29/2013 |
| 8362593 | Method for stacking semiconductor dies A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thick... | 01/29/2013 |
| 8344513 | Barrier for through-silicon via A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of t... | 01/01/2013 |
| 8344506 | Interface structure for copper-copper peeling integrity An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowt... | 01/01/2013 |
| 8338945 | Molded chip interposer structure and methods Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are ... | 12/25/2012 |
| 8338884 | Selective epitaxial growth of semiconductor materials with reduced defects A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contac... | 12/25/2012 |
| 8334220 | Method of selectively forming a silicon nitride layer A method for selectively forming a dielectric layer. An embodiment includes forming a dielectric layer, such as an oxide layer, on a semiconductor substrate, depositing a silicon layer on the dielectric layer, and treating the silicon layer with nitrogen, thereby co... | 12/18/2012 |
| 8324731 | Integrated circuit device An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions o... | 12/04/2012 |
| 8322299 | Cluster processing apparatus for metallization processing in semiconductor manufacturing An apparatus includes an enclosure, at least one process chamber, a robot and at least one valve. The enclosure has a gas therein and at least one door configured to cover an opening into the enclosure. The gas includes at least one reduction gas. The robot is dispo... | 12/04/2012 |
| 8319349 | Approach for bonding dies onto interposers A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. Af... | 11/27/2012 |
| 8319342 | Interconnect structures having permeable hard mask for sealing air gap contained by conductive structures A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric... | 11/27/2012 |
| 8294201 | High-k gate dielectric and method of manufacture A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxida... | 10/23/2012 |
| 8293616 | Methods of fabrication of semiconductor devices with low capacitance Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active a... | 10/23/2012 |
| 8294274 | Semiconductor contact barrier System and method for reducing contact resistance and improving barrier properties is provided. An embodiment includes a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between ... | 10/23/2012 |
| 8278679 | LED device with embedded top electrode An LED device and a method of manufacturing, including an embedded top electrode, are presented. The LED device includes an LED structure and a top electrode. The LED structure includes layers disposed on a substrate, including an active light-emitting region. A top... | 10/02/2012 |
| 8278125 | Group-III nitride epitaxial layer on silicon substrate A semiconductor device includes a silicon substrate; silicon faceted structures formed on a top surface of the silicon substrate; and a group-III nitride layer over the silicon faceted structures. The silicon faceted structures are separated from each other, and hav... | 10/02/2012 |
| 8276648 | PVD target with end of service life detection capability A method for forming a tube-based detector for signaling when a PVD target is reduced to a predetermined quantity of the PVD target material includes providing a mold member having an inner molding member and an outer molding member defining a space therebetween, me... | 10/02/2012 |
| 8263462 | Dielectric punch-through stoppers for forming FinFETs having dual fin heights A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin havi... | 09/11/2012 |
| 8264066 | Liner formation in 3DIC structures An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening a... | 09/11/2012 |
| 8247285 | N-FET with a highly doped source/drain and strain booster A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielec... | 08/21/2012 |
| 8236583 | Method of separating light-emitting diode from a growth substrate A method of forming a light-emitting diode (LED) device and separating the LED device from a growth substrate is provided. The LED device is formed by forming an LED structure over a growth substrate. The method includes forming and patterning a mask layer on the gr... | 08/07/2012 |
| 8232201 | Schemes for forming barrier layers for copper in interconnect structures A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-... | 07/31/2012 |
| 8203209 | Bond pad design for reducing the effect of package stress An integrated circuit structure includes a semiconductor substrate, and an active device formed at a front surface of the semiconductor substrate. A bond pad is over the front surface of the semiconductor substrate. The bond pad has a first dimension in a first dire... | 06/19/2012 |
| 8193087 | Process for improving copper line cap formation An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the fi... | 06/05/2012 |
| 8169076 | Interconnect structures having lead-free solder bumps An integrated circuit structure includes a semiconductor substrate, and a polyimide layer over the semiconductor substrate. An under-bump-metallurgy (UBM) has a first portion over the polyimide layer, and a second portion level with the polyimide layer. A first sold... | 05/01/2012 |
| 8154038 | Group-III nitride for reducing stress caused by metal nitride reflector A device structure includes a substrate; a group-III nitride layer over the substrate; a metal nitride layer over the group-III nitride layer; and a light-emitting layer over the metal nitride layer. The metal nitride layer acts as a reflector reflecting the light e... | 04/10/2012 |
| 8148732 | Carbon-containing semiconductor substrate A light-emitting diode (LED) device is provided. The LED device is formed on a substrate having a carbon-containing layer. Carbon atoms are introduced into the substrate to prevent or reduce atoms from an overlying metal/metal alloy transition layer from inter-mixin... | 04/03/2012 |
| 8148826 | Three-dimensional integrated circuits with protection layers A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and ... | 04/03/2012 |
| 8143114 | System and method for source/drain contact processing System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non... | 03/27/2012 |
| 8143162 | Interconnect structure having a silicide/germanide cap layer An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, an... | 03/27/2012 |
| 8138076 | MOSFETs having stacked metal gate electrodes and method MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition pro... | 03/20/2012 |
| 8134163 | Light-emitting diodes on concave texture substrate A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the s... | 03/13/2012 |
| 8134169 | Patterned substrate for hetero-epitaxial growth of group-III nitride film A circuit structure includes a substrate and a film over the substrate and including a plurality of portions allocated as a plurality of rows. Each of the plurality of rows of the plurality of portions includes a plurality of convex portions and a plurality of conca... | 03/13/2012 |
| 8133097 | Polishing apparatus A chemical mechanical polishing (CMP) device for processing a wafer is provided which includes a plate for supporting the wafer to be processed in a face-up orientation, a polishing head opposing the plate, wherein the polishing head includes a rotatable polishing p... | 03/13/2012 |
| 8125052 | Seal ring structure with improved cracking protection An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circ... | 02/28/2012 |
| 8119500 | Wafer bonding A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support alon... | 02/21/2012 |
| 8109407 | Apparatus for storing substrates An apparatus includes an enclosure and a door configured to seal the enclosure. The door includes a plate. A rotational apparatus is disposed over the plate. At least one first member with a first arm extends from a first rib of the first member. At least one second... | 02/07/2012 |
| 8110890 | Method of fabricating semiconductor device isolation structure A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or mor... | 02/07/2012 |
