Inventor: Bradley S. Masters

Address: Chino, CA
No. of patents: 2
Last patent issue date: 06/20/1989

Number	Title	Issue Date
4841174	CMOS circuit with racefree single clock dynamic logic Disclosed is an improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors, respectively, separated by clocked inverters. The circuit employs a single clock signal to synchroni...	06/20/1989
4740721	Programmable logic array with single clock dynamic logic Disclosed is a programmable logic array employing dynamic CMOS logic and utilizing a single clock signal and its complement to synchronize said dynamic logic operations. The PLA disclosed employs two logic planes for implementing arbitrary logic equations...	04/26/1988

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