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| Number | Title | Issue Date |
| 7743168 | PLL/DLL dual loop data synchronization A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual ... | 06/22/2010 |
| 7194059 | Method and apparatus for skip-free retiming transmission of digital information A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The re... | 03/20/2007 |
| 6975494 | Method and apparatus for providing wideband power regulation to a microelectronic device A method, apparatus, and system for providing operating power and transient suppression power to a microelectronic device are disclosed. The system includes a primary regulator to supply nominal operating power and to respond to relatively slow transient events and ... | 12/13/2005 |
| 6965502 | System, device and method for providing voltage regulation to a microelectronic device The present invention provides a power regulation system and method with high speed signal settling capabilities for providing rapid active transient response to a microelectronic device. An active transient response system includes a power supply configured to rece... | 11/15/2005 |
| 6937685 | Apparatus and method for counting high-speed early/late pulses from a high speed phase detector using a pulse accumulator The method and device according to the present invention provides a control system, method and apparatus for synchronizing a reference signal to high frequency data signals. Pulses are accumulated before reaching the integrator. Pulse accumulation is provided in a D... | 08/30/2005 |
| 6909265 | Method, apparatus and system for predictive power regulation to a microelectronic circuit A transient suppression system is configured for providing power regulation to a microelectronic device. A pre-adjust stage is configured to pre-charge or pre-discharge a bypass capacitor as driven by a predictive transient event signal and in anticipation of a tran... | 06/21/2005 |
| 6809504 | Dual loop regulator A dual loop regulator is configured for improved regulation of a supply voltage for a dynamic load based on the magnitude of changes in the load voltage. An exemplary dual loop regulator comprises a primary voltage regulator configured within a linear loop and a sec... | 10/26/2004 |
| 6794900 | Method and circuit for pre-emphasis equalization in high speed data communications A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an inp... | 09/21/2004 |
| 6791302 | Methods and apparatus for open-loop enhanced control of power supply transients A system is provided for supplying current to a dynamic load subject to transient current requirements. A sense unit coupled to the dynamic load is configured to sense the rate of change of supply current required by the dynamic load during a transient event. A curr... | 09/14/2004 |
| 6670858 | High speed voltage-controlled ring oscillator A high speed ring voltage-controlled oscillator (VCO) system is provided. The ring VCO system includes a plurality of interpolation stages coupled in a "look-ahead" configuration. Each interpolation stage receives two signal inputs and outputs a single di... | 12/30/2003 |
| 6642799 | Phase lock loop destress circuit An improved phase lock loop destress circuit is described. The PLL circuit includes a loop destress logic circuit and a coarse tune digital-to-analog converter, which are coupled to a summer and driver, which in turn is coupled to a voltage controlled osc... | 11/04/2003 |
| 6570406 | Method and circuit for pre-emphasis equalization in high speed data communications A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by recei... | 05/27/2003 |
