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| Number | Title | Issue Date |
| 7661039 | Self-synchronizing bit error analyzer and circuit A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler t... | 02/09/2010 |
| 7404115 | Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator... | 07/22/2008 |
| 6535862 | Method and circuit for performing the integrity diagnostic of an artificial neural network A diagnostic method engages all the neurons of an artificial neural network (ANN) based on mapping an input space defined by vector components based on category, context, and actual field of influence (AIF). The method includes the steps loading the compo... | 03/18/2003 |
| 6523018 | Neural chip architecture and neural networks incorporated therein The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the f... | 02/18/2003 |
| 6502083 | Neuron architecture having a dual structure and neural networks incorporating the same The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block sub... | 12/31/2002 |
| 6377941 | Implementing automatic learning according to the K nearest neighbor mode in artificial neural networks A method of achieving automatic learning of an input vector presented to an artificial neural network (ANN) formed by a plurality of neurons, using the K nearest neighbor (KNN) mode. Upon providing an input vector to be learned to the ANN, a Write compone... | 04/23/2002 |
| 5717832 | Neural semiconductor chip and neural networks incorporated therein A base neural semiconductor chip (10) including a neural network or unit (11(#)). The neural network (11(#)) has a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals.... | 02/10/1998 |
| 5710869 | Daisy chain circuit for serial connection of neuron circuits Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits form a chain. The daisy chain circuit distinguishes between the two possible states of the neuron circuit (engaged or free) and identifies ... | 01/20/1998 |
| 5701397 | Circuit for pre-charging a free neuron circuit In each neuron in a neural network of a plurality of neuron circuits either in an engaged or a free state, a pre-charge circuit, that allows loading the components of an input vector (A) only into a determined free neuron circuit during a recognition phas... | 12/23/1997 |
| 5621863 | Neuron circuit In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to bu... | 04/15/1997 |
| 5463574 | Apparatus for argument reduction in exponential computations of IEEE standard floating-point numbers An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with |x| | 10/31/1995 |
| 5452241 | System for optimizing argument reduction A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system. A partial remainder operation is set forth for high accuracy reduction of polynomials whose arguments are greater than pi/4. The m... | 09/19/1995 |
| 5337265 | Apparatus for executing add/sub operations between IEEE standard floating-point numbers A numeric data coprocessor having an execution unit adapted to efficiently execute addition/subtraction operations on floating-point numbers in compliance with the IEEE standard 754. The mantissa adder carry out bit resulting from the operation on two ope... | 08/09/1994 |
