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| Number | Title | Issue Date |
| 7715410 | Queueing system for processors in packet routing operations In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inser... | 05/11/2010 |
| 7661112 | Methods and apparatus for managing a buffer of events in the background A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a n... | 02/09/2010 |
| 7551626 | Queueing system for processors in packet routing operations In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inse... | 06/23/2009 |
| 7502876 | Background memory manager that determines if data structures fits in memory with memory state transactions map A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map associated with the memory, and a communication link to a processor. Th... | 03/10/2009 |
| 7406586 | Fetch and dispatch disassociation apparatus for multi-streaming processors A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one ... | 07/29/2008 |
| 7139898 | Fetch and dispatch disassociation apparatus for multistreaming processors A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one ... | 11/21/2006 |
| 7058064 | Queueing system for processors in packet routing operations In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inse... | 06/06/2006 |
| 7043467 | Wire-speed multi-dimensional packet classifier For routing packets by rules in a packet network, a system and method in a routing device for selecting rules to apply to packets having each N fields in a header, considers rules as entities in N-dimensional space, projects the rules onto N-axes in the space, marks... | 05/09/2006 |
| 7032226 | Methods and apparatus for managing a buffer of events in the background A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a n... | 04/18/2006 |
