Inventor: Satyanarayana V. Nitta

Address: Poughquag, NY
No. of applications: 39
Last application issue date: 01/10/2013

Application No.	Application Title	Issue Date
20130012017	MICROELECTRONIC STRUCTURE INCLUDING AIR GAP A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The ...	01/10/2013
20130009282	MICROELECTRONIC STRUCTURE INCLUDING AIR GAP A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The ...	01/10/2013
20120329287	LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a...	12/27/2012
20120306018	BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor dev...	12/06/2012
20120301706	METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES A method of depositing a SiN_xC_yliner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiN_xC_yliner on a surface of a low-k substrate having p...	11/29/2012
20120280398	METHOD FOR AIR GAP INTERCONNECT INTEGRATION USING PHOTO-PATTERNABLE LOW K MATERIAL Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods desc...	11/08/2012
20120261828	INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL An interconnect structure includes a patterned and cured dielectric layer located directly on a surface of a patterned permanent antireflective coating. The patterned and cured dielectric layer and the permanent antireflective coating form shaped openings. The shaped op...	10/18/2012
20120111825	AIR GAP INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielect...	05/10/2012
20120068344	INTERCONNECT STRUCTURE WITH A PLANAR INTERFACE BETWEEN A SELECTIVE CONDUCTIVE CAP AND A DIELECTRIC CAP LAYER A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and t...	03/22/2012
20120038056	INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an ...	02/16/2012
20120032311	MULTI COMPONENT DIELECTRIC LAYER An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second time...	02/09/2012
20110272810	STRUCTURE AND METHOD FOR AIR GAP INTERCONNECT INTEGRATION Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods desc...	11/10/2011
20110266682	MICROELECTRONIC STRUCTURE INCLUDING AIR GAP A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The ...	11/03/2011
20110260326	STRUCTURES AND METHODS FOR AIR GAP INTEGRATION Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods desc...	10/27/2011
20110227232	CRENULATED WIRING STRUCTURE AND METHOD FOR INTEGRATED CIRCUIT INTERCONNECTS A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches h...	09/22/2011
20110221062	METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods desc...	09/15/2011
20110111590	DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub...	05/12/2011
20110092067	AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and cont...	04/21/2011
20110003402	RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the n...	01/06/2011
20100285667	METHOD TO PRESERVE THE CRITICAL DIMENSION (CD) OF AN INTERCONNECT STRUCTURE A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, ...	11/11/2010
20100187689	SEMICONDUCTOR CHIPS INCLUDING PASSIVATION LAYER TRENCH STRUCTURE An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer an...	07/29/2010
20100055442	METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES A method of depositing a SiN_xC_yliner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiN_xC_yliner on a surface of a low-k substrate having p...	03/04/2010
20100041227	METHODS FOR INCORPORATING HIGH DIELECTRIC MATERIALS FOR ENHANCED SRAM OPERATION AND STRUCTURES PRODUCED THEREBY Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of ...	02/18/2010
20090311859	METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY A method of fabricating an interconnect structure on a substrate includes steps of: providing a dielectric with at least one etched opening; filling the at least one etched opening with at least one conductive material; planarizing the conductive material to provide a p...	12/17/2009
20090294982	INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an inter...	12/03/2009
20080284039	INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an inter...	11/20/2008
20080265382	Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least ...	10/30/2008
20080265415	Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least ...	10/30/2008
20080254630	DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator laye...	10/16/2008
20080122103	EMBEDDED NANO UV BLOCKING BARRIER FOR IMPROVED RELIABILITY OF COPPER/ULTRA LOW K INTERLEVEL DIELECTRIC ELECTRONIC DEVICES An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films i...	05/29/2008
20070259516	Multilayer interconnect structure containing air gaps and method for making A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive via...	11/08/2007
20070161226	Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is cap...	07/12/2007
20070138640	RECOVERY OF HYDROPHOBICITY OF LOW-K AND ULTRA LOW-K ORGANOSILICATE FILMS USED AS INTER METAL DIELECTRICS Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the n...	06/21/2007
20060103023	Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid...	05/18/2006
20050272341	Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub...	12/08/2005
20050233597	Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least ...	10/20/2005
20050208430	Method of producing self-aligned mask in conjuction with blocking mask, articles produced by same and composition for same A method of forming a self aligned pattern on an existing pattern on a substrate including applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the s...	09/22/2005
20050208752	METHOD FOR FABRICATING A SELF-ALIGNED NANOCOLUMNAR AIRBRIDGE AND STRUCTURE PRODUCED THEREBY A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub...	09/22/2005
20050106762	Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the n...	05/19/2005

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Inventor: Satyanarayana V. Nitta