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Inventor: Ovidiu Bajdechi


Address: Delft, NL
No. of applications: 7
Last application issue date: 10/16/2008

Application No.Application TitleIssue Date
20080253356METHOD AND SYSTEM FOR A POWER REDUCTION SCHEME FOR ETHERNET PHYS
Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T...
10/16/2008
20070296456Low-power ethernet transmitter
An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage m...
12/27/2007
20070273442High-efficiency class-AB amplifier
A high efficiency class-AB amplifier is disclosed. The amplifier comprises a first input stage and a second input stage, both coupled to a class-AB biasing mesh and an output stage, wherein the outputs of the first and second input stages are directly coupled to the out...
11/29/2007
20070273444Techniques for enabling a 10BT active output impedance line driver using a low power supply
A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The ...
11/29/2007
20070176664Programmable gain attenuator for track and hold amplifiers
A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier....
08/02/2007
20070176666Level translator for adapting a signal to a voltage level
A level translator for translating a digital signal from a first voltage level to another voltage level having a higher voltage assigned to the high state of the signal comprises a latch and a pair of N-MOS transistors being coupled to the latch. This design is improved...
08/02/2007
20070035423Method for calibrating a multi-bit digital-to-analog converter, multi-bit digital-to-analog converter in with this method is applied and converter provided with such a multi-bit digital-to-analog converter
In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as Σ Δ ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an addit...
02/15/2007
 
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