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Inventor: Noboru Hirakawa


Address: Tokyo, JP
No. of patents: 3
Last patent issue date: 10/02/1990

NumberTitleIssue Date
4961104Multi-level wiring structure of semiconductor device
For preventing a thin wiring layer from destruction, a multi-level wiring structure incorporated in a semiconductor device is fabricated on a semiconductor substrate. It includes a first insulating layer formed on the semiconductor substrate, a first-leve...
10/02/1990
4878105Semiconductor device having wiring layer composed of silicon film and aluminum film with improved contact structure thereof
A semiconductor device having a wiring layer composed of a polycrystalline silicon film and an aluminum film is disclosed. The wiring layer is provided on an insulating layer with the silicon film and the aluminum film formed on and having the same patter...
10/31/1989
4590508MOS static ram with capacitively loaded gates to prevent alpha soft errors
A semiconductor device in which a logic information can be held stably without being influenced by ଱-rays, is disclosed. The major feature of the device resides in that a capacitor is provided at a control terminal of a transistor holding a logic in...
05/20/1986
 
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