Inventor: Chengwen Pei

Address: Danbury, CT,
No. of applications: 3
Last application issue date: 10/01/2009

Application No.	Application Title	Issue Date
20090242953	SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well hav...	10/01/2009
20090101956	EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device r...	04/23/2009
20090051002	ELECTRICAL FUSE HAVING A THIN FUSELINK A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuseli...	02/26/2009

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