Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 7525346 | Driver circuits and methods In one system embodiment, the system is characterized by: a differential amplifier including but not limited to at least one amplifying transistor having an emitter coupled directly to a ground. In one embodiment of a method of making a system, the method is charact... | 04/28/2009 |
| 7525353 | Brown out detector A brown out detector includes a first resistive element connected to a first voltage and a first node. A capacitor is connected to the first node and a second voltage. The detector also includes a second transistor and a third transistor. The second transistor has a... | 04/28/2009 |
| 7511538 | Data input buffer in semiconductor device A data input buffer in a semiconductor is capable of avoiding operation speed deterioration of the data input buffer due to the temperature condition or process characteristic. The data input buffer in a semiconductor device includes an input detecting unit for dete... | 03/31/2009 |
| 7492198 | Phase-locked loop circuit, delay locked loop circuit, timing generator, semiconductor test instrument, and semiconductor integrated circuit A PLL and DLL are designed such that the power consumption is reduced, the size is reduced, the band width of the locked loop is increased, and the reliability is improved. There are provided a phase comparator for measuring the value of a feedback signal in synchro... | 02/17/2009 |
| 7477091 | Defect tolerant redundancy Circuits, methods, and apparatus for using redundant circuitry on integrated circuits in order to increase manufacturing yields. One exemplary embodiment of the present invention provides a circuit configuration wherein functional circuit blocks in a group of circui... | 01/13/2009 |
| 7477081 | Pre-driver circuit and data output circuit using the same Provided is a pre-driver circuit having a pull-up unit for receiving a data signal, as an input, to output a logical High; a pull-down unit for receiving the data signal, as an input, to output a logical Low; and a control unit for using a control signal reflecting ... | 01/13/2009 |
| 7474136 | Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not use the falling edge of the input clock to provide a reference for the ... | 01/06/2009 |
| 7471118 | Squelch detection system for high speed data links An apparatus comprising a first comparator circuit, a second comparator circuit, a third comparator circuit, and a difference circuit. The first comparator circuit may be configured to generate a first intermediate current in response to a first input voltage and a ... | 12/30/2008 |
| 7459965 | Semiconductor integrated circuit The invention provides a semiconductor integrated circuit of which malfunction caused by noise from outside is reduced. The semiconductor integrated circuit has a power supply terminal, a ground terminal, internal circuits supplied with a power supply potential and ... | 12/02/2008 |
| 7460634 | Shift register circuit Each stage of a shift register circuit has a first input (Rn−1) connected to the output of the preceding stage, a drive transistor (Tdrive)for coupling a first clocked power line voltage (Pn) to the output (Rn) of the st... | 12/02/2008 |
| 7460633 | Folding portable electronic device with storage compartment A pedometer or other portable electronic device may include substantially triangular first and second sections hinged together along a diagonal. A storage compartment is provided in one or both of the sections. The storage compartment may be accessed when the first ... | 12/02/2008 |
| 7459945 | Gate driving circuit and gate driving method of power MOSFET A gate driving circuit and method which increases the switching frequency by use of a switching control circuit which controls operations of a first, second, third, and fourth switches. The switching control circuit performs switching control of a power MOSFET when ... | 12/02/2008 |
| 7459947 | Radio frequency doubler When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signa... | 12/02/2008 |
| 7453973 | Diagnostic method and apparatus for non-destructively observing latch data The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selec... | 11/18/2008 |
| 7453293 | High frequency divider state correction circuit The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled... | 11/18/2008 |
| 7453291 | Switch linearized track and hold circuit for switch linearization Circuits that provide a gate boost to address non-linear threshold voltage variation in a CMOS T/H circuit. In embodiments of the invention, a boost capacitor and a feedback amplifier add a signal-dependent threshold voltage to the switch gate over-drive voltage of ... | 11/18/2008 |
| 7450681 | Shift register A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generati... | 11/11/2008 |
| 7450680 | Fractional-N divider configurable as a polynomial function for real-time PLL swept frequency applications This invention adds a non-linear sweep accumulator to the conventional sigma-delta fractional-N divider to produce a N.F value that is a polynomial function of time. This allows any non-linear sweep profiles to be approximated. ... | 11/11/2008 |
| 7449935 | Driven circuit of an emitter switching configuration to control the saturation level of a power transistor when used with highly variable collector currents A drive circuit for an emitter switching configuration of transistors having a cascode connection of a power bipolar transistor and of a power MOS transistor control the saturation level of the configuration in applications which provide highly variable collector cu... | 11/11/2008 |
| 7446592 | PVT variation detection and compensation circuit A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensat... | 11/04/2008 |
| 7446575 | Capacitor charging methods and apparatuses that use a secure parallel monitoring circuit A capacitor charging circuit and method including a plurality of serially connected capacitors and parallel monitor circuits connected in parallel on a one-to-one basis to the capacitors. Each one of parallel monitor circuits applies a direct-current source voltage ... | 11/04/2008 |
| 7443943 | Shift register A shift register includes a first node controller disposed at one side of the non-display region, the first node controller controlling a signal state of a first node, at least one pull-up switching device disposed at the one side of the display region, the pull-up ... | 10/28/2008 |
| 7443212 | Semiconductor integrated circuit controlling output impedance and slew rate The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in pa... | 10/28/2008 |
| 7440534 | Master-slave flip-flop, trigger flip-flop and counter A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-sl... | 10/21/2008 |
| 7439782 | Semiconductor integrated circuit device with power-on reset circuit for detecting the operating state of an analog circuit A semiconductor integrated circuit device operates using a first power supply and a second power supply differing from the first power supply in voltage. The semiconductor integrated circuit device includes a first detecting circuit which detects that the first powe... | 10/21/2008 |
| 7439776 | Technique to increase the speed of a peak detector A peak detector can advantageously increase its bandwidth, i.e. its charging and discharging speed, while minimizing the ripple of its output signal by sensing the charging current of a storage device. In response to that charging current, the peak detector can cont... | 10/21/2008 |
| 7436221 | Methods and apparatus for ultra-low leakage analog storage An analog storage cell circuit includes a switch that minimizes subthreshold conduction and diode leakage, as well as an accumulation-mode coupling mechanism to minimize overall switch leakage to minimize accumulation-mode leakage. In one embodiment, an analog stora... | 10/14/2008 |
| 7436231 | Low power and low timing jitter phase-lock loop and method A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. Th... | 10/14/2008 |
| 7436242 | System and method for providing an input voltage invariant current source A system and method is disclosed for providing a current source that has an approximately constant value of output current over a range of supply voltages. The current source of the invention comprises a plurality of peaking current source circuits coupled in parall... | 10/14/2008 |
| 7436223 | Technique for improving negative potential immunity of an integrated circuit An integrated circuit (IC) with negative potential protection includes a switch, a gate drive circuit and a comparator. The switch includes a double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-t... | 10/14/2008 |
| 7429886 | Poly fuse trimming circuit A poly fuse trimming circuit. The poly fuse trimming circuit comprises a poly fuse and a silicon controlled rectifier (SCR) device. The poly fuse is coupled between a first fixed potential and an output node. The SCR device is controlled by a trimming signal and has... | 09/30/2008 |
| 7430268 | Dynamic shift register with built-in disable circuit A disable circuit for using in a dynamic shift register unit comprising: a first input, a second input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, and six transistors. The di... | 09/30/2008 |
| 7427881 | Clock loss detection and switchover circuit In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense ci... | 09/23/2008 |
| 7425855 | Set/reset latch with minimum single event upset A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in... | 09/16/2008 |
| 7425851 | Phase-locked loop with incremental phase detectors and a converter for combining a logical operation with a digital to analog conversion The invention relates to a phase-locked loop comprising a voltage controlled oscillator and having a frequency control input for controlling the frequency of the output signal. The phase-locked loop also has a phase comparator for deriving a control signal from a ph... | 09/16/2008 |
| 7425860 | Level converting circuit A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a... | 09/16/2008 |
| 7423463 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 09/09/2008 |
| 7424087 | Clock divider A clock divider includes a first state storage unit, a second state storage unit a first control signal generating unit a state update unit and an output unit. The first state storage unit receives an update signal to perform transition of a first state value in syn... | 09/09/2008 |
| 7423458 | Multiple sampling sample and hold architectures A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling... | 09/09/2008 |
| 7423462 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 09/09/2008 |
