Celebrity Inventors
Superstar singer Michael Jackson co-patented a "Method and means for creating anti-gravity illusion" in 1993.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7463529 | Word line driving circuit putting word line into one of high level, low level and high impedance A word line driving circuit has a main word driver for producing first and second main word driver output signals and a subsidiary word driver for driving a word line. The subsidiary word driver has a load transistor supplied with the first main word driver output s... | 12/09/2008 |
| 7462527 | Method of forming nitride films with high compressive stress for improved PFET device performance A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the P... | 12/09/2008 |
| 7463544 | Device programmable to operate as a multiplexer, demultiplexer, or memory device A device that is programmable to operate as a memory device, a multiplexer, or a demultiplexer includes: a first column decoder; a memory array coupled to the first column decoder; a plurality of selectors coupled to the memory array; and a second column decoder cou... | 12/09/2008 |
| 7463511 | Phase change memory device using multiprogramming method A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit... | 12/09/2008 |
| 7461414 | Simplified bidet assembly for use with a conventional toilet The invention is a bidet assembly that can be easily installed onto any existing conventional toilet. The bidet assembly provides enhanced ease of use, is ergonomically designed and aesthetically pleasing. Furthermore the bidet assembly may be formed from preexistin... | 12/09/2008 |
| 7462548 | Substrate provided with an alignment mark in a substantially transmissive process layer, mask for exposing said mark, device manufacturing method, and device manufactured thereby A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising high reflectance areas for reflecting radiation of an alignment beam of radiation, and low reflectance areas for reflecting less r... | 12/09/2008 |
| 7459399 | Method for manufacturing probe structure of probe card A method for manufacturing a probe structure of a probe card is disclosed. In accordance with the method of the present invention, a dual etching process of a silicon substrate or an etching process of an SOI substrates is carried out using a sidewall insulating fil... | 12/02/2008 |
| 7459348 | Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device formed by stacking a plurality of semiconductor elements on a substrate includes the steps of stacking the plurality of semiconductor elements on the substrate to form plural stages, placing the substrate substantial... | 12/02/2008 |
| 7458110 | Hygienic commode for ladies with reverse sitting A commode chair with reversed seat facing a water tank and with a system for opening the labia of female user for hygienic urination and excretion is provided. The seat assembly including bowl, seat, and lid are formed to support a user to sit on a commode facing th... | 12/02/2008 |
| 7459331 | Micro mirror unit and method of making the same A micro mirror unit includes a moving part carrying a mirror portion, a frame and torsion bars connecting the moving part to the frame. The moving part, the frame and the torsion bars are formed integral from a material substrate. The frame includes a portion thicke... | 12/02/2008 |
| 7458112 | Shower assembly kit with multiple functions A three-way rotary valve is remotely operated by a remote actuator assembly at multiple positions that include diverting flow to: a hand held shower head, an over head fixed shower head, both hand held shower head and over head fixed shower head, and diverting minim... | 12/02/2008 |
| 7454801 | Commodes with user's upper-body support A commode chair with user's upper-body support is provided. The seat assembly of the commode, including bowl, seat, and lid, is formed to support a user to sit on a commode facing the upper-body support. The seating assembly has a narrow width to the direction of th... | 11/25/2008 |
| 7457189 | Integrated circuit memory devices that support selective mode register set commands and related methods A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrat... | 11/25/2008 |
| 7452762 | Thin film transistor and method of fabricating the same The present invention discloses a thin film transistor and a method of fabricating the same. The thin film transistor includes an insulating substrate; and a semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulator, and a source/drain ... | 11/18/2008 |
| 7452149 | Rotating retractable writing instrument The present invention relates to a rotating retractable writing instrument, which is constituted in a simpler way and can thrust a mouthpiece and a writing core element smoothly to positions ready for writing. The writing instrument by the present invention comprise... | 11/18/2008 |
| 7453740 | Method and apparatus for initializing reference cells of a toggle switched MRAM device A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, ... | 11/18/2008 |
| 7453713 | Dual chip package The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second vol... | 11/18/2008 |
| 7452791 | Crystalline semiconductor film, method of manufacturing the same, and semiconductor device A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element soluti... | 11/18/2008 |
| 7453749 | Semiconductor memory device with electrically rewritable and non-volatile memory cells arranged therein A semiconductor memory device includes: a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other; a row decoder configured to drive the word lines; and a sense amp... | 11/18/2008 |
| 7453758 | Control system for a dynamic random access memory and method of operation thereof A dynamic random access memory device includes an array of dynamic random access memory cells subdivided into a group of blocks. Each of the blocks of memory cells can be independently operated in either a single cell mode or a twin cell mode. ... | 11/18/2008 |
| 7449790 | Methods and systems of enhancing stepper alignment signals and metrology alignment target signals Methods and systems of enhancing stepper alignment signals and metrology alignment target signals. In one embodiment, a plurality of alternating rows comprising a first material of a first height and a second material of a second height are constructed. The first ma... | 11/11/2008 |
| 7449378 | Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep... | 11/11/2008 |
| 7450451 | Nonvolatile memory system and method for controlling nonvolatile memory A nonvolatile memory system includes a drive voltage generator to generate a drive voltage on the basis of a power supply voltage; a plurality of normal memory cells serving as a nonvolatile memory storing data by accumulating charge of a polarity according to the d... | 11/11/2008 |
| 7448095 | Time tub A tub having a water holding tank or jacket and a plurality of apertures in the tub so that water from the water jacket can be quickly transferred to the tub and controls within the system to provide means for the user to define water temperature, volume and rate of... | 11/11/2008 |
| 7447067 | Method and apparatus for programming multi level cell flash memory device A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, deter... | 11/04/2008 |
| 7446009 | Manufacturing method for semiconductor device A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partial... | 11/04/2008 |
| 7445951 | Trench photosensor for a CMOS imager A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compare... | 11/04/2008 |
| 7444648 | Fully lazy linking with module-by-module verification A method, computer program, and apparatus verify instructions in a module of a computer program during linking using pre-verification constraints with fully lazy loading. It is first determined whether a first module which is loaded has passed verification one-modul... | 10/28/2008 |
| 7443756 | Memory device having redundancy fuse blocks arranged for testing A method of arranging redundancy fuse block arrays may reduce test time for a memory device. The memory device may include a stack bank structure in which at least two banks share a row decoder or a column decoder. Redundancy fuse block arrays for the two banks may ... | 10/28/2008 |
| 7443727 | Semiconductor memory device having redundancy circuit for replacing a defective part A semiconductor memory device has: a memory cell array including a normal region and a redundancy region; a first decoder configured to decode an address signal to generate a first decode signal; a first driver configured to select a memory cell corresponding to the... | 10/28/2008 |
| 7443036 | Manufacturing method of semiconductor device The manufacturing method of the semiconductor device of the present invention has a step forming solder balls on the circuit face of a mother chip, a step making flip chip bonding of the daughter chip after the step forming solder balls on the circuit face of the mo... | 10/28/2008 |
| 7442570 | Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used ... | 10/28/2008 |
| 7440321 | Multiple select gate architecture with select gates of different lengths A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the fir... | 10/21/2008 |
| 7440392 | Wireless receiver deinterleaver having partitioned memory A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a... | 10/21/2008 |
| 7440337 | Nonvolatile semiconductor memory apparatus having buffer memory for storing a program and buffering work data A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit ( | 10/21/2008 |
| 7436692 | Phase change memory cell with junction selector and manufacturing method thereof A memory cell includes a memory element and a selection element coupled to the memory element. The selection element includes a first junction portion, having a first type of conductivity, and a second junction portion, having a second type of conductivity and formi... | 10/14/2008 |
| 7431524 | Advanced data controlled cleaning system An intelligent cleaning mop is disclosed, which includes a support shaft, a flat mophead connected to the support shaft, a cleaning pad detachably secured to the mophead, a reservoir, a sprayer for spraying cleaning fluid from the reservoir, a power supply device, a... | 10/07/2008 |
| 7433243 | Operation method of non-volatile memory A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the ... | 10/07/2008 |
| 7428168 | Semiconductor memory device sharing a data line sense amplifier and a write driver in order to reduce a chip size A semiconductor memory device includes a first and a second bank, a global data line, a first and a second data line, a data transmitter, and a switch. The global data line is configured between the first and the second banks and commonly shared by the first and the... | 09/23/2008 |
| 7425476 | Manufacturing method of a thin film transistor array panel A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semicon... | 09/16/2008 |
