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| Number | Title | Issue Date |
| 8053847 | Method for fabricating metal-oxide semiconductor transistors A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecu... | 11/08/2011 |
| 8013402 | Transistors with multilayered dielectric films Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises... | 09/06/2011 |
| 8012854 | Semiconductor device and manufacturing method thereof It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Fur... | 09/06/2011 |
| 8008710 | Non-volatile semiconductor storage device A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are f... | 08/30/2011 |
| 7994631 | Substrate for an integrated circuit package and a method of forming a substrate A substrate for an integrated circuit package is disclosed. The substrate comprises a core comprising a first dielectric layer having a first thickness; conductive traces formed on the first dielectric layer for routing signals within the integrated circuit package,... | 08/09/2011 |
| 7989866 | DRAM layout with vertical FETS and method of formation DRAM cell arrays having a cell area of about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The... | 08/02/2011 |
| 7989804 | Test pattern structure A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interf... | 08/02/2011 |
| 7989916 | Integrated capacitors in package-level structures, processes of making same, and systems containing same An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-th... | 08/02/2011 |
| 7982207 | Light emitting diode A light emitting diode (LED) has an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and a transparent electrode layer. The LED includes a tunnel layer interposed between the p-type semiconductor layer and the transparent electrode layer, a... | 07/19/2011 |
| 7977697 | Light emitting device The present invention provides a light emitting device which comprises a light emitting element, a mounting board on which the light emitting element is mounted, a metal-made reflector surrounding the side surfaces of the light emitting element on the mounting board... | 07/12/2011 |
| 7977754 | Poly resistor and poly eFuse design for replacement gate technology A semiconductor device and method for fabricating a semiconductor device is disclosed. The semiconductor device comprises a semiconductor substrate; an active region of the substrate, wherein the active region includes at least one transistor; and a passive region o... | 07/12/2011 |
| 7972935 | Method for manufacturing semiconductor device When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single cry... | 07/05/2011 |
| 7973309 | TEG pattern for detecting void in device isolation layer and method of forming the same Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a f... | 07/05/2011 |
| 7973310 | Semiconductor package structure and method for manufacturing the same Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip s... | 07/05/2011 |
| 7968971 | Thin-body bipolar device A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar de... | 06/28/2011 |
| 7968454 | Method of forming pattern structure A method of forming a pattern structure includes forming a thin film pattern on a substrate, the thin film pattern including depression portions with first bottom widths, forming a protection layer on the thin film pattern by implanting ions into the thin film patte... | 06/28/2011 |
| 7968875 | Organic photosensitive optoelectronic device An organic photosensitive optoelectronic device includes an anode, an organic photosensitive layer formed on the anode and having a donor portion and an acceptor portion, a hole blocking layer formed on the organic photosensitive layer so as for the organic photosen... | 06/28/2011 |
| 7964418 | Real time process monitoring and control for semiconductor junctions A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as... | 06/21/2011 |
| 7964902 | Imaging device First diffusion region constituting a photodiode in each pixel stores carriers generated according to incident light. Second diffusion region is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the periph... | 06/21/2011 |
| 7964909 | Scalable high density non-volatile memory cells in a contactless memory array A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non... | 06/21/2011 |
| 7960835 | Fabrication of metal film stacks having improved bottom critical dimension A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier. ... | 06/14/2011 |
| 7956431 | Method of manufacturing an image sensing micromodule A method of manufacturing a micromodule including the steps of: producing an integrated circuit on an active face of a chip made of a semi-conductive material, making a via passing through the chip, electrically linked to the integrated circuit, and inserting the ch... | 06/07/2011 |
| 7947997 | Semiconductor light emitting device Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active lay... | 05/24/2011 |
| 7939871 | Semiconductor device and manufacturing method thereof The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment... | 05/10/2011 |
| 7936070 | Semiconductor device and method for fabricating semiconductor device A semiconductor device includes: a copper (Cu) wire having a first region and a second region in which densities of silicon (Si) and oxygen (O) atoms are higher than in the first region; a compound film that is selectively formed on the Cu wire and contains Cu and S... | 05/03/2011 |
| 7935982 | Side view type LED package In a side view type light emitting diode (LED) package, a lead frame portion and lead frame electrical contact portions are exposed outside a package body to serve as an additional heat dissipation path. The side view type LED package includes an LED chip, a package... | 05/03/2011 |
| 7928446 | Group III nitride semiconductor substrate and method for cleaning the same A Group-III nitride semiconductor substrate having a flat surface with a dangling bond density of higher than 14.0 nm−2 is produced by cleaning the surface having a dangling bond density of higher than 14.0 nm−2 with a cleaning agent contai... | 04/19/2011 |
| 7923348 | Semiconductor device and manufacturing method thereof It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Fur... | 04/12/2011 |
| 7919825 | Thin film transistors with poly(arylene ether) polymers as gate dielectrics and passivation layers The use of a poly(arylene ether) polymer as a passivation or gate dielectric layer in thin film transistors. This poly(arylene ether) polymer includes polymer repeat units of the following structure: —(O—Ar1—O—Ar2—O—)... | 04/05/2011 |
| 7911029 | Multilayer electronic devices for imbedded capacitor Disclosed herein are multilayer electronic devices comprising a high dielectric constant polymer composite layer that contains conductive components for embedded capacitor applications. ... | 03/22/2011 |
| 7911034 | Techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask... | 03/22/2011 |
| 7906812 | Tunable voltage isolation ground to ground ESD clamp A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the fi... | 03/15/2011 |
| 7906789 | Warm white light emitting apparatus and back light module comprising the same A warm white light emitting apparatus includes a first light emitting diode (LED)-phosphor combination to generatea base light that is white or yellowish white and a second LED-phosphor combination to generate a Color Rendering Index (CRI) adjusting light. The base ... | 03/15/2011 |
| 7902610 | Semiconductor device and method for manufacturing same A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate... | 03/08/2011 |
| 7897961 | Reflex coupler with integrated organic light emitter A reflex coupler has an organic light emitter for generating a light signal and an inorganic photodetector with a detector area. The organic light emitter and the detector area are optically coupled as a result of radiation returned from an object onto which the lig... | 03/01/2011 |
| 7893518 | Method for generating a layout, use of a transistor layout, and semiconductor circuit A method for generating a layout, use of a transistor layout, and semiconductor circuit is provided that includes a matching structure, which has a number of transistors, whose structure is similar to one another, metallization levels with geometrically formed trace... | 02/22/2011 |
| 7888754 | MEMS transducer An MEMS transducer is constituted of a diaphragm, a plate, a support structure for supporting the diaphragm and the plate with a gap layer surrounded by an interior wall, an electrode film (e.g. a pad conductive film) for covering a contact hole formed in the suppor... | 02/15/2011 |
| 7888148 | Signal line for a display device, etchant, thin film transistor panel, and method for manufacturing the same A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the ga... | 02/15/2011 |
| 7888807 | Method of producing wire-connection structure, and wire-connection structure For electrically connecting a wiring formed on one surface of an insulating substrate such as an FPC to an individual electrode arranged facing the other surface of the substrate, firstly, a through hole and a notch are formed by irradiating a laser beam from above ... | 02/15/2011 |
| 7884428 | Semiconductor device and method for manufacturing the same A semiconductor device includes an Nch transistor having a first gate electrode and a Pch transistor having a second gate electrode. The first gate electrode and the second gate electrode are made of materials causing stresses of different magnitudes. ... | 02/08/2011 |
