| Patent No. | Patent Title: |
| 6226214 | Read only memory |
| 6169703 | Method for controlling high speed digital electronic memory |
| 6021084 | Multi-bit block write in a random access memory |
| 6021074 | Direct access to random redundant logic gates by using multiple s... |
| 5982696 | Memories with programmable address decoding and systems and metho... |
| 5978267 | Bit line biasing method to eliminate program disturbance in a ... |
| 5973967 | Page buffer having negative voltage level shifter |
| 5956270 | Flash memory and microcomputer |
| 5930177 | Buffer control circuit and method for semiconductor memory device... |
| 5917759 | Input interface level determiner for use in a memory device |
| 5914907 | Semiconductor memory device capable of increasing chip yields whi... |
| 5912592 | Piezoelectric oscillator |
| 5907510 | Write bias generator for column multiplexed static random access ... |
| 5903509 | Memory device with multiple internal banks and staggered command ... |
| 5903492 | Semiconductor memory device and various systems mounting them |
| 5903505 | Method of testing memory refresh operations wherein subthreshold ... |
| 5903501 | Semiconductor device with 3V/5V tolerant output driver |
| 5898631 | Semiconductor storage |
| 5896344 | Local word line decoder for memory with 2 1/2 MOS devices |
| 5896319 | Current control circuit and non-volatile semiconductor memory dev... |
| 5896339 | Multi-bit block write in a random access memory |
| 5892721 | Parallel test circuit for memory device |
| 5892729 | Power savings for memory arrays |
| 5892716 | Method and apparatus for global testing the impedance of a progra... |
| 5889724 | Word line driving circuit for semiconductor memory device and met... |
| 5889696 | Thin-film capacitor device and RAM device using ferroelectric fil... |
| 5889727 | Circuit for reducing the transmission delay of the redundancy eva... |
| 5889440 | Adaptive frequency compensation technique |
| 5889703 | Data read circuit |
| 5889716 | Semiconductor memory |
| 5889701 | Method and apparatus for selecting optimum levels for in-system ... |
| 5886920 | Variable conducting element and method of programming |
| 5886921 | Static random access memory cell having graded channel metal oxid... |
| 5886930 | Bit interleaving in a memory which uses multi-bit DRAMs |
| 5883830 | CMOS imaging device with integrated flash memory image correction... |
| 5883852 | Configurable SRAM for field programmable gate array |
| 5881011 | Memory device for performing a refresh operation under an active ... |
| 5881010 | Multiple transistor dynamic random access memory array architectu... |
| 5880997 | Bubbleback for FIFOS |
| 5881019 | Synchronous semiconductor memory device capable of improving load... |