| Patent No. | Patent Title: |
| 6303431 | Method of fabricating bit lines |
| 5135882 | Technique for forming high-value inter-nodal coupling resistance ... |
| 5128273 | Method of making a dynamic random access memory cell with stacked... |
| 5128283 | Method of forming mask alignment marks |
| 5126279 | Single polysilicon cross-coupled resistor, six-transistor SRAM ce... |
| 5114873 | Method for manufacturing a stacked capacitor DRAM cell |
| 5108942 | Master slice integrated circuit having a memory region |
| 5108941 | Method of making metal-to-polysilicon capacitor |
| 5106776 | Method of making high performance composed pillar dRAM cell |
| 5104821 | Method for fabricating stacked capacitors in a DRAM cell |
| 5102819 | Method of making a DRAM cell |
| 5100824 | Method of making small contactless RAM cell |
| 5096845 | Method of making field effect transistors in an inner region of a... |
| 5096847 | Method making an ultra high density DRAM cell with stacked capaci... |
| 5094971 | Method of manufacturing a read only semiconductor memory device |
| 5091329 | Method for programming MOS and CMOS ROM memories |
| 5089436 | Method for fabricating a semiconductor device by slope etching a ... |
| 5089434 | Mask surrogate semiconductor process employing dopant-opaque regi... |
| 5087577 | Manufacturing method for a power MISFET |
| 5087588 | Method of making a side wall contact with reactive ion etching |
| 5086008 | Process for obtaining high-voltage N channel transistors particul... |
| 5084418 | Method of making an array device with buried interconnects |
| 5084406 | Method for forming low resistance DRAM digit-line |
| 5084405 | Process to fabricate a double ring stacked cell structure |
| 5082797 | Method of making stacked textured container capacitor |
| 5081059 | Method of forming semiconductor integrated circuit using master s... |
| 5081054 | Fabrication process for programmable and erasable MOS memory devi... |
| 5077228 | Process for simultaneous formation of trench contact and vertical... |
| 5077232 | Method of making stacked capacitor DRAM cells |
| 5075248 | Method of making DRAM having a side wall doped trench and stacked... |
| 5073511 | Method for manufacturing a conductivity modulation MOS semiconduc... |
| 5073515 | Method for manufacturing a trench capacitor of a one-transistor m... |
| 5071783 | Method of producing a dynamic random access memory device |
| 5068199 | Method for anodizing a polysilicon layer lower capacitor plate of... |
| 5068200 | Method of manufacturing DRAM cell |
| 5066606 | Implant method for advanced stacked capacitors |
| 5066603 | Method of manufacturing static induction transistors |
| 5066609 | Method of manufacturing a semiconductor device including a trench... |
| 5066607 | Method of making a trench DRAM cell with dynamic gain |
| 5066608 | Method of making a DRAM cell with stacked trench capacitor |
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