Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 4424576 | Maintenance panel for communicating with an automated maintenance system Apparatus for entering encoded data, command, and address information via a keyboard for transfer to an automated maintenance system designed to perform certain tests on or cause selected events in a unit of a data processing system such as the central pr... | 01/03/1984 |
| 4386403 | System and method for LSI circuit analysis A system and method for analysis of circuits which include a large number of circuit elements. Blocks of circuitry which define logical circuit functions such as gates and latches are set up as macromodels. Each macromodel need be represented in its full ... | 05/31/1983 |
| 4378589 | Undirectional looped bus microcomputer architecture A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one o... | 03/29/1983 |
| 4375078 | Data transfer control circuit This circuit provides a minimally sized bidirectional asynchronous automatic interface between a high speed data processing system and one of a plurality of data terminal devices.... | 02/22/1983 |
| 4374417 | Method for using page addressing mechanism In a computer system, paging operates and a method of use thereof are provided for extending the addressing capability of a processor by using a page register. The page register includes means for storing different codes for different operations to be per... | 02/15/1983 |
| 4371952 | Diagnostic circuitry for isolating a faulty subsystem in a data processing system A data processing system that has a plurality of subsystems connected to a system bus includes diagnostic circuitry for isolating a fault at one of the subsystems. The diagnostic circuitry includes a multiplexer at the output gates of each subsystem to th... | 02/01/1983 |
| 4368515 | Bank switchable memory system A decoding circuit is coupled to the signal lines that communicate address signals to a memory unit. When a predetermined address is communicated, the decoding circuit produces a supplemental signal that is coupled to the memory unit and used to select on... | 01/11/1983 |
| 4368514 | Multi-processor system There is disclosed a multi-processor system having a master processor and a plurality of slaves. Each processor is provided with its own memory. Although each slave processor can access only its respective memory, the master processor can access either it... | 01/11/1983 |
| 4367525 | CPU Channel monitoring system A computer monitoring system connects into the channel (24), serving as a link between a CPU (10) and peripheral devices (12), (14), (16). Channel signals are extracted in a channel interface module (18), altered to be compatible with the logic in a data ... | 01/04/1983 |
| 4365292 | Array processor architecture connection network A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection n... | 12/21/1982 |
| 4365296 | System for controlling the duration of the time interval between blocks of data in a computer-to-computer communication system System for controlling the duration of the time interval between the blocks of data transmitted by a computer 1. A channel 7 transfers the first block to be transmitted to a control unit 2 which sends same over a line 4 through a modem 3. When the block h... | 12/21/1982 |
| 4363091 | Extended address, single and multiple bit microprocessor The addressable memory space within the retrievable capacity of the microprocessor is necessarily limited by the bit length of the address word. This in turn, is limited by the bit length of the word which the microprocessor may compute or manipulate. By ... | 12/07/1982 |
| 4363108 | Low cost programmable video computer terminal There is disclosed herein an apparatus for displaying data and communicating with another data processing device via a parallel port or over a long distance communications network via a full duplex modem, said computer terminal utilizing a microprocessor ... | 12/07/1982 |
| 4361877 | Billing recorder with non-volatile solid state memory A billing recorder for providing a record of customer usage of electricity has a controller which may include a microprocessor for receiving and processing pulses from an electric meter. Data from one or more input channels is temporarily stored in random... | 11/30/1982 |
| 4360868 | Instruction prefetch means having first and second register for storing and providing a current PC while generating a next PC Microinstruction selection circuitry effects the selection of successive microinstructions of a sequence. Current and next PCs are stored in first and second registers. Current PC is provided to a memory from one register to fetch a current instruction fr... | 11/23/1982 |
| 4358823 | Double redundant processor A double redundant processor including first and second master processors for processing data, control and address signals in a data processing system. The first master processor is in an active state for processing the signals and the second master proce... | 11/09/1982 |
| 4358829 | Dynamic rank ordered scheduling mechanism A mechanism is provided which permits the insertion of elements into a list of positions determined by the rank of the elements and allows deletion of elements only from the top of the list. The arrangement provides dynamic aging of the priorities of the ... | 11/09/1982 |
| 4357656 | Method and apparatus for disabling and diagnosing cache memory storage locations In a data processing system having a main memory containing addressable main memory storage locations, and also having a processor with a cache memory containing addressable cache memory storage locations, signals representative of predetermined addressab... | 11/02/1982 |
| 4356546 | Fault-tolerant multi-computer system A Fault-Tolerant Multi-Computer System for control applications is disclosed. The system has a plurality of Computers (10a-10n), each having an assigned set of tasks which it is capable of executing. No one Computer in the system acts as a master and no o... | 10/26/1982 |
| 4355369 | Automatic banking machine A high speed, computer controlled banding machine provides fully automated teller stations for completing banking functions in response to a coded credit card presented thereto. A complete banking system normally consists of four remote terminals (custome... | 10/19/1982 |
| 4353077 | Optical floppy disc data storage and retrieval techniques An optical floppy disc constructed of microfilm, thermoplastic or paper and bears digital and/or graphic information. Digital information may be stored in radial lines each of which comprises the digital information to be retrieved and line addresses at t... | 10/05/1982 |
| 4348720 | Microcomputer arranged for direct memory access A microcomputer system arranged for performing direct memory access operations has direct memory access circuitry included on a single chip with the main processor of the microcomputer. Addressing for direct memory access operations is accomplished by cir... | 09/07/1982 |
| 4348741 | Priority encoder Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel outpu... | 09/07/1982 |
| 4347568 | Occupational health/environmental surveillance A method and computer system manipulates data concerning the health of a plurality of employees, each of the employees working in at least one work location and being identifiable by an employee identification, each of the work locations being identifiabl... | 08/31/1982 |
| 4345309 | Relating to cached multiprocessor system with pipeline timing A cached multiprocessor system operates in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds t... | 08/17/1982 |
| 4344131 | Device for reducing the time of access to information contained in a memory of an information processing system A circuit arrangement for reducing access time to information contained in a memory system that includes a register for collecting the information contained in the memory system. The register operates as a flip-flop and is composed of a first inverter, an... | 08/10/1982 |
| 4344129 | Data processor system capable of providing both a computer mode and a sequencer mode of operation A data processor system is capable of operating in a first mode comprising a computer mode so as to carry out data processing functions and is also capable of operating in a second mode comprising a sequencer mode so as to carry out high speed sequence op... | 08/10/1982 |
| 4342095 | Computer terminal A computer terminal is disclosed which may advantageously be employed as a video display terminal having editing capabilities. The terminal is a processor driven terminal having a common bus architecture. This includes a central processing unit CPU having... | 07/27/1982 |
| 4342080 | Computer with microcode generator system A computer system which includes an improved apparatus for generating microcode instructions to produce a starting address. A portion of the address information is applied to a plurality of banks of memory and another portion of the address is used to ena... | 07/27/1982 |
| 4342078 | Instruction register sequence decoder for microprogrammed data processor and method A data processor which includes an instruction register for storing a macroinstruction to be executed, a decoder responsive to the stored macroinstruction for generating two or more starting addresses, and a selector which receives the starting addresses ... | 07/27/1982 |
| 4339793 | Function integrated, shared ALU processor apparatus and method A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one o... | 07/13/1982 |
| 4338663 | Calling instructions for a data processing system A digital data processing system with a central processor for responding to diverse instructions including instructions for calling subroutines. When the central processor executes a calling instruction, the central processor saves information correspondi... | 07/06/1982 |
| 4336588 | Communication line status scan technique for a communications processing system A communication processor is coupled to recognize and handle on a priority basis, service interrupt requests from a plurality of communication line adapters. The processor is also adapted to perform a firmware-controlled scan of the communication line ada... | 06/22/1982 |
| 4335446 | Terminal equipment for data-transmission network including digitally operating modem At a subscriber station AU communicating with a central office of a data network, a logic unit UM includes a processing subunit UE which, under the control of a microprogrammed subunit UC comprising a microinstruction memory MM and a sequencer SQ, digital... | 06/15/1982 |
| 4335448 | Electronic control system An electronic control system particularly suited for use with an automatic fuel dispensing system uses a centrally located computer to supply serial polling signals to various sub-stations. At the sub-stations, the polling signals are decoded into signals... | 06/15/1982 |
| 4334268 | Microcomputer with branch on bit set/clear instructions A single-chip microcomputer comprises a central processor unit (100), a random access memory (110), a read only memory (120), internal timing circuitry including a timer counter (131), and three I/O data ports (140, 150, and 160). Included within the inst... | 06/08/1982 |
| 4332009 | Memory protection system A memory protect circuit (12) is provided for protecting inadvertent alteration of data stored in a data storage unit (32) of a data processing system (10). The data processing system (10) includes a microprocessor (14) for generating an address signal to... | 05/25/1982 |
| 4330824 | Universal arrangement for the exchange of data between the memories and the processing devices of a computer An interface for the exchange of data between memories and processing devices of a computer, which interface does not depend on any particular technology of the processing and memory units and which is readily adaptable to units having different timing fo... | 05/18/1982 |
| 4328557 | Processor circuit for video data terminal An electronic data processor, for use with a keyboard, a telephone set and a standard television receiver, for permitting the exchange of data with an information system. The electronic processor includes circuitry for displaying pages of alphanumeric tex... | 05/04/1982 |
| 4328542 | Secure implementation of transition machine computer A secure implementation of a transition machine utilizing requirements oriented application programming and a hardware executive. The hardware executive is physically separate and protected from data processors executing the application programs and limit... | 05/04/1982 |
