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| Number | Title | Issue Date |
| 6608774 | Two-photon four-dimensional optical memory Selected domains, normally 2×103×2×10.sup.3 such domains arrayed in a plane, within a three-dimensional (3-D) volume of radiation-sensitive medium, typically 1 cm3 of spirobenzopyran containing 2×103 such planes, are t... | 08/19/2003 |
| 6504774 | DDR SDRAM for stable read operation A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the... | 01/07/2003 |
| 6483735 | Two-photon, three-or four-dimensional, color radiation memory Three-, and four-dimensional ("3-D" and "4-D") volume radiation memories store multiple binary bits of information--typically about five to ten and more typically eight such bits--in the same physical volumes on several different photochromic chemicals co... | 11/19/2002 |
| 6459641 | Semiconductor memory device The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present in... | 10/01/2002 |
| 6414871 | Systems and methods for programming programmable devices Programmable devices and methods of programming programmable devices are described. In one embodiment, a complex programmable logic device (CPLD) is programmed by a remote host programming unit that provides the configuration data over a data communicatio... | 07/02/2002 |
| 6400612 | Memory based on a four-transistor storage cell A memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second termin... | 06/04/2002 |
| 6396760 | Memory having a redundancy scheme to allow one fuse to blow per faulty memory column An apparatus and method in which a single fuse is asserted in a memory bank having a redundancy memory column structure. The assertion of the single fuse causes two or more of the input-output circuits to shift away from a primary memory column to a subst... | 05/28/2002 |
| 6392936 | Method and apparatus for generating from a single supply line voltages internal to a flash memory with reduced settling times Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted ref... | 05/21/2002 |
| 6392947 | Semiconductor memory device To efficiently access pixel data stored in memory in the X direction and Y direction when carrying out error correction processing. In a data output section 10, a pixel block consisting the desired 2×2 pixel data W1-W4 is selected by inputting a address,... | 05/21/2002 |
| 6381172 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used f... | 04/30/2002 |
| 6377495 | Apparatus and method for providing a bias to read memory elements A method and apparatus for dynamically determining when a bias circuit has reached a steady-state operation so that the memory elements (e.g., EPROMs) may be read. The bias circuit includes a read enable circuit, a bias circuit, and an output circuit. The... | 04/23/2002 |
| 6377500 | Memory system with a non-volatile memory, having address translating function Logical block addresses are allocated to the blocks provided on a flash memory, respectively. Address translation tables (LTPb's) are provided on the flash memory, each for a group of blocks. Groups of logical block addresses are provided, each group for ... | 04/23/2002 |
| 6377484 | Embedded electrically programmable read only memory devices The present invention provides novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. The... | 04/23/2002 |
| 6366525 | Semiconductor memory of the dynamic random access type (DRAM) and method for actuating a memory cell A semiconductor memory of the dynamic random access type (DRAM) includes memory cells combined in addressable units of bit lines and word lines. Each memory cell array is allocated a row decoder for selection of one of the word lines and a column decoder ... | 04/02/2002 |
| 6363026 | Address generating device for use in multi-stage channel interleaver/deinterleaver An address generating device for addressing data stored in an interleaver memory in B rows and F columns, where F is not 2k for a positive integer k. A row counter being responsive to B clock pulses, outputs carry signal when the row counter co... | 03/26/2002 |
| 6359812 | Memory device A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input ... | 03/19/2002 |
| 6356475 | Ferroelectric memory and method of reading out data from the ferroelectric memory A method of reading data from a ferroelectric memory has a memory cell which uses a ferroelectric capacitor as a storage medium. The method includes the steps of (a) applying first and second electric fields having opposite directions to the ferroelectric... | 03/12/2002 |
| 6356497 | Graphics controller integrated circuit without memory interface A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display... | 03/12/2002 |
| 6356495 | Memory array architecture, method of operating a dynamic random access memory, and method of manufacturing a dynamic random access memory A dynamic random access memory includes a plate line; a digit line; a memory cell selectively coupled between the digit line and the plate line; sense circuitry selectively coupled to the memory cell to read the memory cell and capable of applying a first... | 03/12/2002 |
| 6356484 | Semiconductor memory device A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in eac... | 03/12/2002 |
| 6356486 | Electrically alterable non-volatile memory with n-bits per cell An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The p... | 03/12/2002 |
| 6353554 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals are dependent upon the levels of programming reference signals used for ... | 03/05/2002 |
| 6353569 | Semiconductor memory device A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster th... | 03/05/2002 |
| 6349058 | Electronic circuit and method for storing configuration and calibration information in a non-volatile memory array An electronic circuit includes a non-volatile memory that has several memory cells. The output of the non-volatile memory is connected to the inputs of several latches. Each latch has an output adapted to be read independently. A refresh circuit is connec... | 02/19/2002 |
| 6344998 | Electrically alterable non-volatile memory with N-Bits per cell An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The p... | 02/05/2002 |
| 6343034 | Electrically alterable non-volatile memory with n-bits per cell An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The p... | 01/29/2002 |
| 6341095 | Apparatus for increasing pulldown rate of a bitline in a memory device during a read operation An apparatus for increasing pulldown rate of a bitline in a memory device during a read operation is disclosed. The memory device includes a pair of complementary differential bitlines, and each of the complementary differential bitlines has a precharge t... | 01/22/2002 |
| 6339544 | Method to enhance performance of thermal resistor device An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and ... | 01/15/2002 |
| 6339545 | Electrically alterable non-volatile memory with n-bits per cell An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The p... | 01/15/2002 |
| 6335884 | Semiconductor memory device and defect remedying method thereof Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged i... | 01/01/2002 |
| 6335896 | Dynamic random access memory A capacitor memory data storage system of reading, writing and refreshing which uses short bit line segments separated by pass transistors to allow smaller capacitors and faster speeds than the prior art.... | 01/01/2002 |
| 6331960 | Nonvolatile semiconductor memory device and method for using the same A nonvolatile semiconductor memory device includes nonvolatile memory cells (C), constant voltage circuits for applying one of different verify voltages to control gates of the nonvolatile memory cells C in response to control data introduced into the mem... | 12/18/2001 |
| 6331953 | Intelligent ramped gate and ramped drain erasure for non-volatile memory cells A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage acros... | 12/18/2001 |
| 6331942 | Content addressable memory cell and design methodology utilizing grounding circuitry A CAM cell design methodology and a method of pre-charge and comparison timing is disclosed. A CAM cell utilizing this design methodology includes grounding circuitry and a P-channel transistor configured to communicate a comparison result to a match line... | 12/18/2001 |
| 6330205 | Virtual channel synchronous dynamic random access memory The present invention provides a semiconductor memory device comprising: memory cells; main decoders decoding address signals sense amplifiers for reading out informations from the memory cells; and word drivers for driving the memory cells, wherein a row... | 12/11/2001 |
| 6330203 | Test mode for verification of on-chip generated row addresses Described is a method for verification of proper address generation in packet based memory protocol (Direct RDRAM) devices during the auto-refresh or self-refresh cycle that does not require changes to the interface logic or core signal generation. The me... | 12/11/2001 |
| 6327179 | Semiconductor memory device and method for producing same There is provided a semiconductor memory device using a three-layer gate electrode material film to improve yields and reliability, and a method for producing the same. A floating gate 4 of a memory transistor MT is formed of a first-layer gate electrode ... | 12/04/2001 |
| 6327188 | Synchronous random access memory An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and ... | 12/04/2001 |
| 6327193 | Mixed signal method for display deflection signal generation for low cost displays Vertical rate deflection signals are generated using a combination of digital and analog techniques. A signal is generated by a switched capacitor type accumulator circuit, a wave shape control circuit, and a DC signal centering circuit. The signal is per... | 12/04/2001 |
| 6327204 | Method of storing information in a memory cell A method of storing information in a memory cell. The method writes information via only the bit-line that is connected to a memory cell with respect to a word-line, and thus reduces the overall power consumption in the memory by reducing the unnecessary ... | 12/04/2001 |
