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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 7464130 | Logic circuit and method for performing AES MixColumn transform A logic circuit having structure for performing the AES Rijndael MixColumns transform exploits the relationship between each successive row of the transform matrix and its preceding row. Multiplication of an (m×n) matrix by a (1×n) or by a (m×1) matrix is perform... | 12/09/2008 |
| 7464131 | Logical calculation circuit, logical calculation device, and logical calculation method A logical calculation circuit capable of storing data, and performing logical calculations with high reliability and high speeds are provided. The residual polarized state s′ of a load ferroelectric capacitor Cs′ is actively changed so that the residual polarize... | 12/09/2008 |
| 7464128 | Methods and apparatus for single stage Galois field operations Techniques for single function stage Galois field (GF) computations are described. The new single function stage GF multiplication requires only m-bits per internal logic stage, a savings of m−1 bits per logic stage that do not have to be accounted for as compared... | 12/09/2008 |
| 7461108 | Barrel shift device When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a second shift circuit 50 using a decoding circuit 20, it... | 12/02/2008 |
| 7457838 | Methods and apparatus for performing calculations using reduced-width data Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width d... | 11/25/2008 |
| 7454451 | Method for finding local extrema of a set of values for a parallel processing element A method for finding a local extrema for a single processing element having a set of values associated therewith includes separating the set of values into an odd set of values and an even set of values, determining a first extrema from the odd set of values, determ... | 11/18/2008 |
| 7451174 | Multi-level soft detector-quantizer An analog electronic circuit is proposed that e.g. computes the symbol likelihoods for PAM or QAM signal constellations. The circuit has at least one set of M transistors connected to a common current source. A multiplier/adder generates the voltages to be applied t... | 11/11/2008 |
| 7451171 | Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root operations. Exemplary embodiments include a method including receiving a first microcoded instruction in the pipeline, decoding the first microco... | 11/11/2008 |
| 7447719 | Quantum computing method and quantum computer An (N+1) number of physical systems each having five energy levels |0>, |1>, |2>, |3>, and |4>, a qubit being expressed by |0> and |1>, are provided in an optical cavity having a cavity mode resonant with |2>-|3>, such that an N number of control systems and a targe... | 11/04/2008 |
| 7447720 | Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each of the processing elements a dimensional extrema for a first dimension of the n-dimensional array, wherein the dimension... | 11/04/2008 |
| 7447721 | Method and apparatus for generating true random numbers by way of a quantum optics process A method and apparatus for generating true random numbers by way of a quantum optics process uses a light source to produce a beam which illuminates a detector array. The detectors of the array are associated with random numbers values. Detection of a photon by one ... | 11/04/2008 |
| 7444367 | Floating point status information accumulation circuit A floating point flag combining or accumulating circuit includes an analysis circuit that receives a plurality of floating point operands, each having encoded status flag information, and a result assembler. The analysis circuit analyzes the plurality of floating po... | 10/28/2008 |
| 7437391 | Numerically controlled oscillator and method of operation In one embodiment, the present invention is directed to a numerically controlled oscillator. The numerically controlled oscillator comprises: a phase accumulator for receiving an input digital word; and a phase to amplitude converter that is operatively coupled to t... | 10/14/2008 |
| 7437398 | Pattern matching architecture A pattern matching unit includes a selection unit to divide an input datum and one or more reference templates into input bit-fields corresponding reference bit-fields, respectively. The number of bits in the input and reference bit-fields is programmable. A distanc... | 10/14/2008 |
| 7437402 | Low-power, high-speed word comparator Apparatus and method for performing a high-speed, low-power bit-wise comparison of two digital words. For each bit, a bit comparator is shown, employing a compare node and a discharge node. After both nodes are charged, the discharge node is discharged and the condi... | 10/14/2008 |
| 7437399 | Method and apparatus for averaging parity protected binary numbers A method and an apparatus for averaging includes generating a carry using a least significant bit of each of two binary numbers, wherein the two binary numbers include a first binary number and a second binary number, and adding a first shifted binary number, a seco... | 10/14/2008 |
| 7437395 | FFT operating apparatus of programmable processors and operation method thereof A fast Fourier transform (FFT) operating apparatus and a method thereof carries out an FFT operation in a programmable processor chip. A program controller generates an FFT start signal and controls a programmable processor, and a program memory stores an applicatio... | 10/14/2008 |
| 7433905 | Device and method for processing digital values in particular in non-adjacent form A table establishes correspondence between first sets of at least one number, expressed in accordance with a signed code where each number may have the value of 0, 1 or −1, and second sets of at least one number, expressed according to a simple form where each num... | 10/07/2008 |
| 7433909 | Processing architecture for a reconfigurable arithmetic node A computational unit, or node, in a adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection ... | 10/07/2008 |
| 7430577 | Computationally efficient mathematical engine A method and system for performing many different types if algorithms utilizes a single mathematical engine such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively contr... | 09/30/2008 |
| 7430575 | One-dimensional fourier transform program, method and apparatus A one-dimensional Fourier transform program for quickly performing a one-dimensional Fourier transform intended for a scalar computer comprises a step of resolving a data length N of one-dimensional data into the product of factors N1×N2×. . ... | 09/30/2008 |
| 7428561 | Apparatus and method for scaling digital data information A data processing apparatus for scaling a digital data source is provided. The data processing apparatus includes a ratio transformation module and a scaling module. The ratio transformation module receives a ratio signal and generates a Look-up Table (LUT). The sca... | 09/23/2008 |
| 7428564 | Pipelined FFT processor with memory address interleaving A fast Fourier transform processor using a single delay path and a permuter provides a reduction in the implementation area and a related reduction in power consumption through efficiencies obtained by the modification of a butterfly unit and the use of a novel inte... | 09/23/2008 |
| 7428567 | Arithmetic unit for addition or subtraction with preliminary saturation detection An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithm... | 09/23/2008 |
| 7428563 | Apparatus and method for selectively performing Fast Hadamard Transform or Fast Fourier Transform Disclosed is an apparatus for performing both FHT (Fast Hadamard Transform) and FFT (Fast Fourier Transform). This apparatus determines the phase coefficients as constantly “1” when performing the FHT, and changes the input order of input data to a reverse order... | 09/23/2008 |
| 7426529 | Processor and method for a simultaneous execution of a calculation and a copying process A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in eac... | 09/16/2008 |
| 7426527 | Random number generator and method for generating a random number Random number generator having a transistor that generates an analog random telegraph signal (RTS) having a first or second signal state, a RTS detection unit for detecting the RTS generated by the transistor, a RTS sampling unit that supersamples the RTS detected b... | 09/16/2008 |
| 7424503 | Pipelined accumulators Pipelined digital accumulators. Parallel digital accumulators for use in digital signal processing are improved through pipelining. An accumulator is partitioned into a plurality of pipelined stages, and the pipeline delay is used to reduce the effect of carry propa... | 09/09/2008 |
| 7424508 | Self-timed carry look-ahead adder and summation method thereof A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a M... | 09/09/2008 |
| 7424501 | Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations Nonlinear filtering and deblocking applications utilizing SIMD (single instruction multiple data) sign and absolute value operations are disclosed. The method of one embodiment includes receiving first data for a first block and second data for a second block. The f... | 09/09/2008 |
| 7424504 | Arithmetic processor for accomodating different field sizes An arithmetic processor is provided, which comprises an arithmetic logic unit (ALU) containing arithmetic circuitry configured to perform field operations in an underlying field. The circuitry comprises a first controller for sequencing the ALU through steps in the ... | 09/09/2008 |
| 7424507 | High speed, low power, pipelined zero crossing detector that utilizes carry save adders A zero crossing detector employs carry save adders combined with fully pipelined logic to provide two-bit, three-bit or four-bit zero crossing detection. The detector offers the advantages of very high operating speed, very low power dissipation, low adder cell coun... | 09/09/2008 |
| 7424505 | Method and apparatus for performing multiply-add operations on packed data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor p... | 09/09/2008 |
| 7421463 | Random sequence generating apparatus, encryption/decryption apparatus, random sequence generating method, encryption/decryption method and program Disclosed is a random sequence generating apparatus for generating a sequence of integers. A seed receiving section receives a sequence of integers as a seed. An initialization section provides a transformation section with the received sequence of integers. The tra... | 09/02/2008 |
| 7421464 | System and method for introducing dither for reducing spurs in digital-to-time converter direct digital synthesis A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305).... | 09/02/2008 |
| 7418469 | Method and apparatus for adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control Various components of the present invention are collectively designated as Adaptive Real-Time Embodiments for Multivariate Investigation of Signals (ARTEMIS). It is a method, processes, and apparatus for measurement and analysis of variables of different type and or... | 08/26/2008 |
| 7415495 | Selective filter having linear phase A method for determining a filter that is very selective and having linear phase is described. The method starts with choosing a pole constellation in the complex frequency plane in a unique manner so that a desired passband phase of the filter is linear while prese... | 08/19/2008 |
| 7412473 | Arithmetic circuitry for averaging and methods thereof A functional unit includes one or more instances of arithmetic circuitry for calculating averages. Each instance of arithmetic circuitry includes first, second and third adders, each having first and second inputs and an output that is a sum of the first and second ... | 08/12/2008 |
| 7412471 | Discrete filter having a tap selection circuit A digital signal processing circuit includes a chain of processing units having a selectable number of taps and a tap selection circuit. The tap selection circuit is coupled to the chain of processing units to establish the number of taps of the chains. ... | 08/12/2008 |
| 7409417 | Polyphase filter with optimized silicon area A polyphase filter including M taps, each of the M taps including a filter coefficient. The filter also includes a multiplier-accumulator (MAC) shared by the M taps, a plurality of multiplexors for sequentially selecting a subset of the plurality of taps, and a sche... | 08/05/2008 |
