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| Number | Title | Issue Date |
| 8189398 | Read operation method of memory device A read operation method of a memory device includes applying a first voltage to each of a first memory cell and a second memory cell during a first read operation, applying the first voltage to the first memory cell and a second voltage to the second memory cell dur... | 05/29/2012 |
| 8189287 | Equalization and minimization of multi-head stack assembly's motion during self servo writing and HDD operation A disk hard disk drive that includes a spindle motor and an actuator arm coupled to a base plate. A plurality of disks are coupled to the spindle motor and a plurality of heads are coupled to the actuator arm and the disks. The drive also includes a cover attached t... | 05/29/2012 |
| 8189374 | Memory device including an electrode having an outer portion with greater resistivity A memory cell includes a first electrode having a first region and a second region, a second electrode and a phase change material. The phase change material is interposed between the first electrode and the second electrode with the first region of the first electr... | 05/29/2012 |
| 8189387 | Flash memory with multi-bit read A memory device is described that comprises determining which read data state of more than 2X read data states a memory cell is in after the memory cell has been programmed to one of 2X program data states, wherein the determined read data stat... | 05/29/2012 |
| 8184493 | Semiconductor memory device and system A semiconductor memory device includes a memory cell array including primary word lines and one or more redundant word lines, a timing signal generating circuit configured to generate a refresh timing signal comprised of a series of pulses arranged at constant inter... | 05/22/2012 |
| 8184496 | Semiconductor device and method for operating the same A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming v... | 05/22/2012 |
| 8179639 | Head gimbal assembly without bus traces for plating Head gimbal assemblies for data storage systems are provided. Some embodiments include a dielectric layer having a first and a second side. A first conductive layer is on the first dielectric layer. The first conductive layer includes a pad and a trace. A second con... | 05/15/2012 |
| 8174899 | Non-volatile semiconductor memory device When data is written to a memory cell transistor, a write controller controls in such a manner that a verification operation subsequent to a program operation is carried out while a program voltage is increased stepwise for each program operation. The write controll... | 05/08/2012 |
| 8174796 | Baseplate interconnect An actuator and associated method is provided, the actuator having an arm defining an aperture, an electrical circuit supported by the arm and terminating at a contact, a flexure assembly defining a boss and supporting a second electrical circuit terminating at a se... | 05/08/2012 |
| 8174868 | Embedded SRAM structure and chip An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is... | 05/08/2012 |
| 8169842 | Skew detector and semiconductor memory device using the same A skew detection circuit includes a data sensing block configured to sense a first data that is transferred earliest and a last data that is transferred latest among a plurality of data which are transferred through different transfer paths, and generate a sensing r... | 05/01/2012 |
| 8164963 | Semiconductor memory device A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in... | 04/24/2012 |
| 8164940 | Read/write structures for a three dimensional memory Read/write structures for three-dimensional memories are disclosed. In one embodiment, a three-dimensional memory includes a plurality of data storage layers fabricated in parallel on top of one another to form a three-dimensional structure. Each data storage layer ... | 04/24/2012 |
| 8159880 | NAND flash memory In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the me... | 04/17/2012 |
| 8159869 | Circuit and method for generating reference voltage, phase change random access memory apparatus and read method using the same A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write dri... | 04/17/2012 |
| 8154825 | Magnetic recording head and magnetic recording device It is made possible to provide a magnetic head that can stabilize the high-frequency magnetic field generated from the spin torque oscillator. A magnetic head includes: first and second main magnetic poles; and a spin torque oscillator provided between the first and... | 04/10/2012 |
| 8149645 | Synchronous global controller for enhanced pipelining The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller ... | 04/03/2012 |
| 8149625 | Nonvolatile memory device, operating method thereof, and memory system including the same A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the st... | 04/03/2012 |
| 8144518 | Semiconductor device The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of ... | 03/27/2012 |
| 8144531 | Latency control circuit, semiconductor memory device including the same, and method for controlling latency A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information r... | 03/27/2012 |
| 8144493 | CAM cell memory device A code address memory (CAM) cell memory device comprises a first storage unit comprising a first nonvolatile memory cell configured to output a power source voltage in response to a read voltage, and a second storage unit comprising a second nonvolatile memory cell ... | 03/27/2012 |
| 8139419 | Programming methods and memories Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and ... | 03/20/2012 |
| 8139412 | Systematic error correction for multi-level flash memory In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuit... | 03/20/2012 |
| 8139402 | Magnetic memory device A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed... | 03/20/2012 |
| 8134886 | Method and apparatus for reducing oscillation in synchronous circuits Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filt... | 03/13/2012 |
| 8130542 | Reading non-volatile multilevel memory cells Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an... | 03/06/2012 |
| 8130560 | Multi-rank partial width memory modules A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number ... | 03/06/2012 |
| 8125822 | Reducing programming time of a memory cell The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, c... | 02/28/2012 |
| 8120975 | Memory having negative voltage write assist circuit and method therefor A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that is lower t... | 02/21/2012 |
| 8116114 | Semiconductor memory and system A pair of access control circuits having bit line pairs wired corresponds to a same data terminal and is assigned different addresses. During a test mode, a data swap circuit prohibits swapping of connections between a pair of data terminals and a pair of data lines... | 02/14/2012 |
| 8116157 | Integrated circuit An integrated circuit is disclosed. One embodiment provides a sense amplifier; a first bit line; a second bit line. A first switch is configured to connect/disconnect the first bit line to/from the sense amplifier. A second switch is configured to connect/disconnect... | 02/14/2012 |
| 8116042 | Magnetoresistance device A device capable of exhibiting the extraordinary magnetoresistance (EMR) effect includes an elongate channel formed of silicon. A conductor comprising heavily doped silicon is connected to the channel along one side of the channel so as to provide a shunt. A gate ar... | 02/14/2012 |
| 8111575 | Semiconductor device There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and... | 02/07/2012 |
| 8107270 | Three dimensional hexagonal matrix memory array A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithogra... | 01/31/2012 |
| 8107189 | Device and structure for reducing tape motion and static friction A tape mounting apparatus for a magnetic tape data storage device which includes a movable structure movably attached to a base. The movable structure moves partially within the base and is powered by a motor unit. The moveable structure has at least a load position... | 01/31/2012 |
| 8107308 | Semiconductor memory device A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs... | 01/31/2012 |
| 8107285 | Read direction for spin-torque based memory device A spin-torque based memory device includes a plurality of magnetic storage cells in an array, each magnetic storage cell includes at least one magnetic tunnel junction (MTJ) element, and at least one bit line and at least one bit complement line corresponding to the... | 01/31/2012 |
| 8103822 | Method and apparatus for implementing a caching policy for non-volatile memory The present disclosure relates to methods, devices and computer-readable medium for implementing a caching policy and/or a cache flushing policy in a peripheral non-volatile storage device operatively coupled to a host device. In some embodiments, data is stored to ... | 01/24/2012 |
| 8102719 | Semiconductor memory device capable of compensating variation with time of program voltage A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage ge... | 01/24/2012 |
| 8094417 | Magnetoresistance device A magnetoresistance device has a channel extending between first and second ends in a first direction comprising non-ferromagnetic semiconducting material, such as silicon, a plurality of leads connected to and spaced apart along the channel, a gate structure for ap... | 01/10/2012 |
