U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

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Examiner: Quach, T. N.


Primary examiner statistics: 1111 patents; average approval time: 1111 days
Assistant examiner statistics: 247 patents; average approval time: 609 days

Patents as Primary Examiner (view all)

Patent No. Patent Title:
7768013 Vertical structure thin film transistor
7408193 Semiconductor device and manufacturing method thereof
7391075 Non-volatile semiconductor memory device with alternative metal g...
7388276 Metal-insulator varactor devices
7372103 MOS field plate trench transistor device
7371599 Image sensor and method of forming the same
7372101 Sub-lithographics opening for back contact or back gate
7372089 Solid-state image sensing device
7368758 Method for hermetically housing optical components, and optical c...
7368774 Capacitor and its manufacturing method, ferroelectric memory devi...
7368347 Dual bit flash memory devices and methods for fabricating the sam...
7365418 Multi-chip structure
7361988 Apparatuses and methods to route line to line
7361954 Power semiconductor device
7358558 Flash memory device
7358560 Flash memory device and method of manufacturing the same
7358530 Thin-film transistor array with ring geometry
7358565 Semiconductor device having improved insulated gate bipolar trans...
7355241 Non-volatile memory
7355277 Apparatus and method integrating an electro-osmotic pump and micr...
7355234 Semiconductor device including a stacked capacitor
7355225 Semiconductor device and method for providing a reduced surface a...
7355276 Thermally-enhanced circuit assembly
7348613 CMOS imager with selectively silicided gates
7338862 Methods of fabricating a single transistor floating body DRAM cel...
7339229 Nonvolatile memory solution using single-poly pFlash technology
7339215 Transistor device containing carbon doped silicon in a recess nex...
7339236 Semiconductor device, driver circuit and manufacturing method of ...
7339232 Semiconductor device having multi-bit nonvolatile memory cell and...
7339223 Semiconductor devices having dual capping layer patterns and meth...
7335532 Method of assembly for multi-flip chip on lead frame on overmolde...
7335543 MOS device for high voltage operation and method of manufacture
7329914 Charge trapping memory device with two separated non-conductive c...
7326952 Elevated pore phase-change memory
7323749 Semiconductor device comprising an integrated circuit
7323783 Electrode, method for producing same and semiconductor device usi...
7320910 Semiconductor device
7321147 Semiconductor device including a trench capacitor
7319252 Methods for forming semiconductor wires and resulting devices
7315057 Split gate non-volatile memory devices and methods of forming sam...

Patents as Assistant Examiner (view all)

Patent No. Patent Title:
5196358 Method of manufacturing InP junction FETS and junction HEMTS usin...
5130274 Copper alloy metallurgies for VLSI interconnection structures
5114879 Method of forming a microelectronic contact
5106765 Process for making a BiMOS
5104823 Monolithic integration of optoelectronic and electronic devices
5102826 Method of manufacturing a semiconductor device having a silicide ...
5098854 Process for forming self-aligned silicide base contact for bipola...
5098861 Method of processing a semiconductor substrate including silicide...
5098862 Method of making ohmic electrical contact to a matrix of semicond...
5096843 Method of manufacturing a bipolar CMOS device
5094983 Method for manufacture of an integrated MOS semiconductor array
5094965 Field effect transistor having substantially coplanar surface str...
5094964 Method for manufacturing a bipolar semiconductor device
5091325 Process for making MOS devices for low-temperature operation
5089430 Method of manufacturing semiconductor integrated circuit bipolar ...
5089431 Method of manufacturing a semiconductor device including a static...
5089428 Method for forming a germanium layer and a heterojunction bipolar...
5089438 Method of making an article comprising a TiNx layer
5089429 Self-aligned emitter BiCMOS process
5086007 Method of manufacturing an insulated gate field effect transistor
5086016 Method of making semiconductor device contact including transitio...
5082800 Method of forming pattern in manufacturing semiconductor device
5081053 Method for forming a transistor having cubic boron nitride layer
5081065 Method of contacting silicide tracks
5081066 Method for forming a silicide film used in a semiconductor chip
5075237 Process of making a high photosensitive depletion-gate thin film ...
5071789 Method for forming a metal electrical connector to a surface of a...
5066602 Method of making semiconductor IC including polar transistors
5064773 Method of forming bipolar transistor having closely spaced device...
5064775 Method of fabricating an improved polycrystalline silicon thin fi...
5063167 Method of producing a bipolar transistor with spacers
5063168 Process for making bipolar transistor with polysilicon stringer b...
5061645 Method of manufacturing a bipolar transistor
5059547 Method of manufacturing double diffused MOSFET with potential bia...
5059553 Metal bump for a thermal compression bond and method for making s...
5059554 Method for forming polycrystalline silicon contacts
5057455 Formation of integrated circuit electrodes
5057443 Method for fabricating a trench bipolar transistor
5057450 Method for fabricating silicon-on-insulator structures
5057454 Process for producing ohmic electrode for p-type cubic system bor...
 
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