U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

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Examiner: Parihar, Suchin


Primary examiner statistics: 51 patents; average approval time: N/A
Assistant examiner statistics: 177 patents; average approval time: 183 days

Patents as Primary Examiner (view all)

Patent No. Patent Title:
8156461 Spice corner model generating method and apparatus
8151226 Coordinated-design supporting apparatus, coordinated-design suppo...
8151219 System and method for multi-exposure pattern decomposition
8151229 System and method of computing pin criticalities under process va...
8146049 Support apparatus and design support method
8146046 Structures for semiconductor structures with error detection and ...
8146036 Circuit for and method of determining a process corner for a CMOS...
8141004 Solution-dependent regularization method for quantizing continuou...
8141015 Reporting status of timing exceptions
8141017 Method for bounded transactional timing analysis
8136054 Compact abbe's kernel generation using principal component analys...
8136068 Methods, systems, and computer program products for implementing ...
8136073 Circuit design fitting
8132136 Dynamic critical path detector for digital logic circuit paths
8117578 Static hazard detection device, static hazard detection method, a...
8112729 Method and system for selective stress enablement in simulation m...
8112724 Method of designing semiconductor integrated circuit, apparatus f...
8104002 Performing logic optimization and state-space reduction for hybri...
8104004 Logic performance in cyclic structures
8104005 Method and apparatus for efficient incremental statistical timing...
8104006 Method and apparatus for thermal analysis
8104007 Method and apparatus for thermal analysis
8104008 Layout design apparatus, layout design method, and computer produ...
8104012 System and methods for reducing clock power in integrated circuit...
8104014 Regular local clock buffer placement and latch clustering by iter...
8104009 Wire mapping for programmable logic devices
8103976 Photo mask set for forming multi-layered interconnection lines an...
8103978 Method for establishing scattering bar rule
8103979 System for generating and optimizing mask assist features based o...
8103987 System and method for managing the design and configuration of an...
8103988 Use of breakouts in printed circuit board designs
8103989 Method and system for changing circuits in an integrated circuit
8103990 Characterising circuit cell performance variability in response t...
8103991 Semiconductor integrated circuit designing method, semiconductor ...
8103992 Rapid rerouting based runtime reconfigurable signal probing
8103993 Structure for dynamically allocating lanes to a plurality of PCI ...
8103994 Generating cutting forms along current flow direction in a circui...
8103995 Method for OPC correction
8103996 Method and apparatus for thermal analysis of through-silicon via ...
8103997 Method of employing slew dependent pin capacitances to capture in...

Patents as Assistant Examiner (view all)

Patent No. Patent Title:
8161430 System and method of resistance based memory circuit parameter ad...
8136067 Method of design for manufacturing
8037433 System and methodology for determining layout-dependent effects i...
8028255 Semiconductor integrated circuit, semiconductor integrated circui...
8028260 Determination of most critical timing paths in digital circuits
8010919 Method for evaluating the quality of a computer program
8001496 Control of design automation process
7992114 Timing analysis using statistical on-chip variation
7984397 Power network stacked via removal for congestion reduction
7984405 Method and apparatus for determining the timing of an integrated ...
7979812 Method and apparatus for correcting assist-feature-printing error...
7979814 Model implementation on GPU
7975247 Method and system for organizing data generated by electronic des...
7971162 Verification of spare latch placement in synthesized macros
7966587 Information storage medium on which is stored an interconnection ...
7958467 Deterministic system and method for generating wiring layouts for...
7949968 Method and system for building binary decision diagrams optimally...
7949966 Data verification method, charged particle beam writing apparatus...
7945874 Method for designing driver
7937673 Method and system for implementing top down design and verificati...
7934178 Layout method of semiconductor circuit, program and design suppor...
7934182 Method and apparatus for supporting delay analysis, and computer ...
7934172 SLM lithography: printing to below K1=.30 without previous OPC pr...
7934180 Incremental speculative merging
7930661 Software model for a hybrid stacked field programmable gate array
7930659 Software verification
7926010 Method of determining defects in photomask
7908574 Techniques for use with automated circuit design and simulations
7900179 Method for prioritizing nodes for rerouting and device therefor
7895551 Generation of standard cell library components with increased sig...
7890906 Method of laying out integrated circuit design based on known pol...
7890909 Automatic block composition tool for composing custom blocks havi...
7890913 Wire mapping for programmable logic devices
7890893 Design structure for semiconductor on-chip repair scheme for nega...
7886237 Method of generating a functional design structure
7886254 Method for amending layout patterns
7886242 Systems, methods, and apparatus for total coverage analysis and r...
7886248 Layout method of semiconductor integrated circuit and computer-re...
7877709 Method of placing wires
7877724 Decision tree representation of a function
 
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