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Examiner: Hu, Shouxiang


Primary examiner statistics: 337 patents; average approval time: 341 days
Assistant examiner statistics: 82 patents; average approval time: 915 days

Patents as Primary Examiner (view all)

Patent No. Patent Title:
8138491 Self-aligned nanotube field effect transistor
8138614 Semiconductor device having an antenna with anisotropic conductiv...
8134168 Group-III nitride semiconductor device
8120153 High-temperature, wirebondless, injection-molded, ultra-compact h...
8115323 Semiconductor package and method of manufacturing the semiconduct...
8101511 Method of manufacturing a junction barrier Schottky diode with du...
8101978 Circuit and photo sensor overlap for backside illumination image ...
8053293 Method of manufacturing a display substrate
8049205 Poly(alkynylthiophene)s and electronic devices generated therefro...
8048781 Methods and systems for packaging integrated circuits
8049202 Phase change memory device having phase change material layer con...
8043977 Method of manufacturing a semiconductor device having a group-III...
8022486 CMOS semiconductor device
8022440 Compound semiconductor epitaxial substrate and manufacturing meth...
8003989 Thin film semiconductor device having a terminal portion
8003533 Method for forming a laminated structure having a wettability-var...
7999324 Semiconductor device including overcurrent protection element
7989828 Highly efficient III-nitride-based top emission type light emitti...
7977672 Organic light-emitting device with field-effect enhanced mobility
7977744 Field effect transistor with trench filled with insulating materi...
7977680 Semiconductor device having thin film transistors on a metal subs...
7977669 Semiconductor memory device having a liquid-repellent layer
7973363 IGBT semiconductor device
7968960 Methods of forming strained semiconductor channels
7960220 Method of forming polysilicon, thin film transistor using the pol...
7951710 Method for manufacturing thin film transistor and display device
7944059 Semiconductor device having a probing region
7939909 Device having inductors and capacitors
7936020 Dual-directional electrostatic discharge protection device
7936048 Power transistor and power semiconductor device
7927989 Method for forming a transistor having gate dielectric protection...
7919834 Edge seal for thru-silicon-via technology
7919787 Semiconductor device with a light emitting semiconductor die
7910913 Phase change memory devices
7902549 Deposition method of insulating layers having low dielectric cons...
7897960 Self-aligned nanotube field effect transistor
7892943 Isolation trenches for memory devices
7893439 Silicon nitride film and semiconductor device
7888667 Phase change memory device
7888268 Method of forming a gate layer with multiple ecthing steps

Patents as Assistant Examiner (view all)

Patent No. Patent Title:
6614082 Fabrication of semiconductor devices with transition metal boride...
6541829 Semiconductor device and method of manufacturing the same
6515339 Method of horizontally growing carbon nanotubes and field effect ...
6504189 Semiconductor device having a microstrip line
6501155 Semiconductor apparatus and process for manufacturing the same
6483147 Through wafer backside contact to improve SOI heat dissipation
6483153 Method to improve LDD corner control with an in-situ film for loc...
6469357 Article comprising an oxide layer on a GaAs or GaN-based semicond...
6465842 MIS semiconductor device and method of fabricating the same
6458697 Semiconductor device and manufacturing method therefor
6455890 Structure of fabricating high gate performance for NROM technolog...
6455912 Process for manufacturing shallow trenches filled with dielectric...
6448587 Circuit incorporated IGBT and power conversion device using the s...
6437418 High quality factor, integrated inductor and production method th...
6436798 MOSFET device
6420777 Dual layer etch stop barrier
6420746 Three device DRAM cell with integrated capacitor and local interc...
6407406 Semiconductor device and method of manufacturing the same
6404025 MOSFET power device manufactured with reduced number of masks by ...
6399989 Radiation hardened silicon-on-insulator (SOI) transistor having a...
6400029 Self-limiting method of reducing contamination in a contact openi...
6396102 Field coupled power MOSFET bus architecture using trench technolo...
6380627 Low resistance barrier layer for isolating, adhering, and passiva...
6376890 High-voltage edge termination for planar structures
6373101 Solid-state relay
6373098 Trench-gated device having trench walls formed by selective epita...
6373095 NVRAM cell having increased coupling ratio between a control gate...
6365912 Superconducting tunnel junction device
6365925 Semiconductor device
6365972 Method for forming a metal wiring structure of a semiconductor de...
6365924 Dual direction over-voltage and over-current IC protection device...
6348709 Electrical contact for high dielectric constant capacitors and me...
6346739 Static charge dissipation pads for sensors
6337496 Ferroelectric capacitor
6337500 Semiconductor device and method for fabricating the same
6316806 Trench transistor with a self-aligned source
6316803 Integrated circuit memory devices having self-aligned contact
6307232 Semiconductor device having lateral high breakdown voltage elemen...
6291837 Substrate of semiconductor device and fabrication method thereof ...
6271575 Method and mask structure for self-aligning ion implanting to for...
 
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