Bizarre Patents
Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8176396 | System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic Various methods and systems for implementing Reed Solomon multiplication sections from exclusive-OR (XOR) logic are disclosed. For example, a system includes a Reed Solomon multiplication section, which includes XOR-based logic. The XOR-based logic includes an input... | 05/08/2012 |
| 8171369 | DTV transmitting system and receiving system and method of processing broadcast data A DTV transmitting system includes a frame encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The frame encoder builds an enhanced data frame and encodes the frame two times for first and second error correction, re... | 05/01/2012 |
| 8171376 | Method for protecting important data of contents and apparatus therefor A method of protecting important data in digital content and an apparatus therefor are provided. The method includes: receiving digital content which includes first important data; receiving reference data which includes second important data and authentication data... | 05/01/2012 |
| 8161346 | Data refresh apparatus and data refresh method According to one embodiment, a data refresh apparatus which refreshes data stored in a storage device having storage areas, comprises an error detector configured to detect a number of errors of data stored in a storage area of the storage device, an error correctio... | 04/17/2012 |
| 8156389 | Pruned bit-reversal interleaver A pruned bit-reversal interleaver supports different packet sizes and variable code rates and provides good spreading and puncturing properties. To interleave data, a packet of input data of a first size is received. The packet is extended to a second size that is a... | 04/10/2012 |
| 8156390 | Pruned bit-reversal interleaver A pruned bit-reversal interleaver supports different packet sizes and variable code rates and provides good spreading and puncturing properties. To interleave data, a packet of input data of a first size is received. The packet is extended to a second size that is a... | 04/10/2012 |
| 8156406 | Method and system for syndrome generation and data recovery A method and system for syndrome generation and data recovery is described. The system includes a parity generator coupled to one or more storage devices to generate parity for data recovery. The parity generator includes a first comparator to generate a first parit... | 04/10/2012 |
| 8151155 | Packet Re-transmission controller for block acknowledgement in a communications system A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with the pointers to be applied to a media access... | 04/03/2012 |
| 8136010 | Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple o... | 03/13/2012 |
| 8136008 | ECC with out of order completion Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, initiating processing of the first data frame through the ECC decoder, receiving a second da... | 03/13/2012 |
| 8132077 | Unidirectional error code transfer for both read and write data transmitted via bidirectional data link A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a por... | 03/06/2012 |
| 8127193 | Methods and apparatus to reduce errors during a re-transmission Methods and apparatus to reduce errors during a re-transmission performed by a communication module are disclosed. An example method includes detecting an error in received data, predicting a time interval that is expected to be substantially error-free, and transmi... | 02/28/2012 |
| 8127194 | Method and apparatus for improving hybrid automatic repeat request operation in a wireless communications system In order to avoid unknown behavior of a user equipment, the present invention provides a method of improving Hybrid Automatic Repeat Request, known as HARQ, operation for a network in a wireless communications system. The method includes adding a HARQ information in... | 02/28/2012 |
| 8127214 | Unified decoder for convolutional, turbo, and LDPC codes A unified decoder is capable of decoding data encoded with convolutional codes, Turbo codes, and LDPC codes. In at least one embodiment, a unified decoder is implemented within a multi-standard wireless device. ... | 02/28/2012 |
| 8127200 | Flash memory device and system with randomizing for suppressing errors A device for storing data includes a nonvolatile memory and a controller and/or circuitry that randomize original data to be stored in the memory while preserving the size of the original data, that store the original data in the memory, and that, in response to a r... | 02/28/2012 |
| 8122331 | Media defect compensation system and method A system and method of media defect compensation incorporate an architecture capable of modifying a signal representative of data reproduced from a recording medium to compensate for defects in the medium. In accordance with one aspect of the invention, a media defe... | 02/21/2012 |
| 8112699 | Error detecting/correcting scheme for memories A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, ... | 02/07/2012 |
| 8108757 | Method for effectively transmitting control signal in wireless communication system A method of performing HARQ performed by a user equipment (UE) is provided. The method includes receiving a bundling indicator which indicates the number of bundled downlink subframes, determining whether at least one bundled downlink subframe is missed by comparing... | 01/31/2012 |
| 8108746 | Radio communications apparatus and radio communications method A disclosed radio communications apparatus performs at least an automatic repeat request control and performs radio communications using a frame that occupies predetermined plural frequency bands. This apparatus includes a reception portion that receives feedback in... | 01/31/2012 |
| 8108754 | Programmable logic device programming verification systems and methods In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The metho... | 01/31/2012 |
| 8108747 | Data repair The invention relates to a method for data repair in a system capable of one-to-many transmission. The method comprises transmitting data from a sender to at least one receiver and provides for various sender driven or receiver driven repair methods of missing data.... | 01/31/2012 |
| 8103930 | Apparatus for implementing processor bus speculative data completion A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrect... | 01/24/2012 |
| 8103932 | DTV transmitting system and receiving system and method of processing broadcast data A DTV transmitting system includes a frame encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The frame encoder builds an enhanced data frame and encodes the frame two times for first and second error correction, re... | 01/24/2012 |
| 8103944 | Memory architecture for high throughput RS decoding for MediaFLO receivers A system and method for increasing the throughput of a RS decoder in MediaFLO™ receivers. A MAC de-interleaver RAM architecture allowing operation of parallel RS decoders comprises of four equal portioned memory banks, a codeword buffer for data correction, and a ... | 01/24/2012 |
| 8103946 | Secure data strategy for vehicle control systems A method of providing secure data from vehicle operational variable data that includes a plurality of data message bits includes the steps of dividing the plurality of data message bits into a first group of data message bits and a second group of data message bits,... | 01/24/2012 |
| 8103945 | Decoding method and decoding apparatus as well as program A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sort... | 01/24/2012 |
| 8095858 | File error identification, reporting, and replacement of media files The present invention discloses a solution for automatically replacing a media files upon a device able to identify problems with locally stored media files. Initially, an automated process or user of a media playing device can initially identify a media file, which... | 01/10/2012 |
| 8095863 | Low complexity decoding of low density parity check codes An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable nod... | 01/10/2012 |
| 8095847 | Exception condition handling at a channel subsystem in an I/O processing system A computer program product, apparatus, and method for handling exception condition feedback at a channel subsystem of an I/O processing system using data from a control unit are provided. The computer program product includes a tangible storage medium readable by a ... | 01/10/2012 |
| 8091008 | Data read-out circuit in semiconductor memory device and method of data reading in semiconductor memory device A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the s... | 01/03/2012 |
| 8086942 | Parallel concatenated code with bypass A method of encoding non-key frame data is disclosed. The method includes forming a bit stream from the data by arranging the bits from the data in a known order. The bit stream is interleaved to form an interleaved bit stream, and parity bits are generated for each... | 12/27/2011 |
| 8086933 | Semiconductor storage device, method of controlling the same, and error correction system A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (S... | 12/27/2011 |
| 8082484 | DTV transmitter and method of coding main and enhanced data in DTV transmitter A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data p... | 12/20/2011 |
| 8082480 | Distributed checksum computation Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data. ... | 12/20/2011 |
| 8078943 | Error correction code for correcting shift and additive errors An error correction system is disclosed comprising an encoder operable to generate an encoded codeword of a polynomial code over a Galois field GF(q) comprising q elements, wherein the encoded codeword comprises an input data sequence, at least one check symbol, and... | 12/13/2011 |
| 8078937 | Memory-module controller, memory controller and corresponding memory arrangement, and also method for error correction A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of... | 12/13/2011 |
| 8078948 | Two-phase data-transfer protocol A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example e... | 12/13/2011 |
| 8074156 | Decoding method and decoding apparatus Disclosed herein is a decoding method of performing maximum a posteriori probability (MAP) decoding of selecting one decoded word from one or more decoded word candidates obtained by subjecting a linear code to iterative decoding by comparison of distances between a... | 12/06/2011 |
| 8074134 | Pattern generator and memory testing device using the same An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that inclu... | 12/06/2011 |
| 8069391 | Error correction using error detection codes A method, apparatus, and computer-readable media comprises receiving a detected sequence representing a signal on a channel, wherein the detected sequence comprises data bits and one or more error detection code bits; receiving one or more error indications for the ... | 11/29/2011 |
