Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
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| Number | Title | Issue Date |
| 6938199 | Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same A recording medium for storing real time recording/reproduction information, a real time recording and reproducing method and apparatus, and a file operating method using the information. Real time recording/reproduction information for ensuring real time recording/... | 08/30/2005 |
| 6915475 | Data integrity management for data storage systems A system and method for maintaining the integrity of data in a storage system. The method includes receiving a plurality of blocks of data having a predetermined multiple-block error detecting code; reading each block of the blocks of data; generating, for each bloc... | 07/05/2005 |
| 6877129 | Method for measuring the receiver-side bit error rate of a DVB transmission system The invention relates to a method for measuring the receiver-side bit error rate of the transmission path of a DVB transmission system in which the data stream to be transmitted is channel-coded on the transmitter side by a Reed-Solomon coder and on the receiver sid... | 04/05/2005 |
| 6877131 | Apparatus and method for generating block code in a mobile communication system An apparatus encodes 7 input bits into 24 symbols in a mobile communication system. In the apparatus, an encoder encodes 7 input bits into 32 symbols using an extended Reed-Muller code created from a Gold sequence, and a puncturer punctures 8 symbols from the 32 sym... | 04/05/2005 |
| 6874116 | Masking error detection/correction latency in multilevel cache transfers A method, and a corresponding apparatus, mask error detection and correction latency during multilevel cache transfers. The method includes the steps of transferring error protection encoded data lines from a first cache, checking the error protection encoded data l... | 03/29/2005 |
| 6829737 | Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results A method and system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test resu... | 12/07/2004 |
| 6820232 | Device and method for detecting errors in CRC code having reverse ordered parity bits A device for detecting in a receiver whether any transmission errors have occurred in the received CRC code, in a case that a transmitter transmits the CRC code created by sequencing the parity bits, which are generated using the generator polynomial, in the reverse... | 11/16/2004 |
| 6813742 | High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture A Bandband Processor for Wireless Communications is presented. The invention encompasses several improved Turbo codes method to provide a more practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP coding. (1) A plurality of pipelined p... | 11/02/2004 |
| 6804803 | Method for testing integrated logic circuits A method of testing a circuit having multiple elements is disclosed. A plurality of faults representing the elements of the circuit for testing said circuit is created. The faults are grouped based on common attributes of the faults. A test pattern for each group of... | 10/12/2004 |
| 6799295 | High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture A baseband processor is provided having Turbo Codes Decoders with Diversity processing for computing signals from separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, ... | 09/28/2004 |
| 6799290 | Data path calibration and testing mode using a data bus for semiconductor memories A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are di... | 09/28/2004 |
| 6799296 | Viterbi detector for optical disk system A high speed Viterbi detector for an optical disk system, includes a frequency dividing unit for generating an auxiliary clock at one-third of the main clock frequency, a branch metric calculation unit for calculating each of a plurality of branch metrics, a serial-... | 09/28/2004 |
| 6792569 | Root solver and associated method for solving finite field polynomial equations An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally us... | 09/14/2004 |
| 6792571 | Viterbi detector for partial response maximum likelihood signal processing A Viterbi detector for use in a partial response maximum likelihood (PRML) signal processing apparatus. The Viterbi detector can be used for different partial response (PR) equalizations with different parameters, and can be used for different PRML signal processing... | 09/14/2004 |
| 6789225 | Bit error position estimation in data decoder A bit error position is estimated. The estimation method includes generating data indicative of a substantial number of bit error locations in data frames. The generation of the data includes re-encoding decoded bit stream, mapping the bit stream to a first set of s... | 09/07/2004 |
| 6785861 | Versatile serial concatenated convolutional codes An input digital signal is encoded by subjecting it to a first convolutional coding step followed by an interleaving step and a second convolutional coding step. The serial concatenated convolutional coded signal thus obtained is then subjected to modulation by mean... | 08/31/2004 |
| 6785856 | Internal self-test circuit for a memory array An integrated memory self-tester that tests an entire memory array reduces the need for sophisticated external test equipment and reduces the duration of the test. A read test of the memory array can check the memory cells. Optional programmable registers may store ... | 08/31/2004 |
| 6779148 | Error detection and correction method in a computer system and main memory controller of the same According to an error detection and correction method to be implemented in a computer system, when an error is detected in data to be written in a memory, fault information is appended to the data without an increase in the number of bits constituting the data, and ... | 08/17/2004 |
| 6775796 | Creation of memory array bitmaps using logical to physical server A method and system for generating memory array bitmaps is disclosed that uses the memory binary address and failing memory data bits collected during test of a chip as input and translates this input directly to physical location in physical design formats which us... | 08/10/2004 |
| 6775803 | Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same A recording medium for storing real time recording/reproduction information, a real time recording and reproducing method and apparatus, and a file operating method using the information. Real time recording/reproduction information for ensuring real time recording/... | 08/10/2004 |
| 6772391 | Hybrid interleaver for turbo codes A turbo code encoder with a hybrid interleaver having two recursive systematic constituent code (RSC) encoders. The system encodes a finite sequence of informative bits without requiring a plurality of tail bits to flush the registers of each encoder to an all-zero ... | 08/03/2004 |
| 6769081 | Reconfigurable built-in self-test engine for testing a reconfigurable memory A reconfigurable built-in self-test (“BIST”) engine for testing a reconfigurable memory is disclosed. The BIST engine executes a test on a memory for detecting faults. If the memory under test fails the test executed by the BIST engine, a decision is made depend... | 07/27/2004 |
| 6760879 | System and method of turbo decoding Methods and architectures for turbo decoding are presented. The methods are such that low energy consumption is obtained with reduced memory requirements. Moreover the methods show improved performance with respect to latency. ... | 07/06/2004 |
| 6754862 | Gaining access to internal nodes in a PLD Internal registers of a PLD are exposed for debugging using a JTAG port and a scan chain. The user of a PLD identifies registers at the source code level. These registers are automatically inserted in a scan chain. An EDA software tool provides a means of choosing a... | 06/22/2004 |
| 6754870 | CRC operation unit and CRC operation method To enable high-speed CRC operation and flexible use of various generating polynomials without causing significant increase in circuit scale, the CRC operation unit uses circuits generally provided for a DSP and some additional circuits. The CRC operation unit includ... | 06/22/2004 |
| 6754872 | Method and apparatus for reducing channel distortion in a wireless communications network A method and apparatus for reducing channel distortion in a broadband, wireless network comprising a residential communications gateway that accepts all incoming communications signals and securely broadcasts those signals throughout a residence. In one embodiment, ... | 06/22/2004 |
| 6751773 | Coding apparatus capable of high speed operation A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on... | 06/15/2004 |
| 6745359 | Method of masking corrupt bits during signature analysis and circuit for use therewith A method of masking corrupt bits in test response pattern scan chains in an integrated circuit, comprising loading and applying a set of test patterns in the scan chains so as to obtain corresponding test response patterns; and masking bits of the test response patt... | 06/01/2004 |
| 6742152 | Parallel scan test software The present invention provides an improved boundary scan test system that can scan device scan paths in a parallel manner. In one embodiment, an improved method for processing a scan command from a pattern file is provided. The scan command is associated with (e.g.,... | 05/25/2004 |
| 6742150 | Low redesign application-specific module The present invention, in addition to the number of connections required for the specified functions of an ASIC, provides an application specific module ASIC that has additional connections as spares for subsequent modification. Buffers, boundary scan devices and, p... | 05/25/2004 |
| 6738937 | Method for nondisruptive testing of device and host attachment to storage subsystems The present invention is directed to a system and method of installing additional devices to storage subsystems without disrupting the overall storage system. The present invention may utilize a storage controller which allows testing of devices while the devices ar... | 05/18/2004 |
| 6738945 | Signal transmission device and method for avoiding transmission error A signal transmission device adapted to transmit an n-bit parallel digital signal is used for avoiding a transmission error. The device includes a detector for receiving a first and a second n-bit digital data consecutively occurred in the n-bit parallel digital sig... | 05/18/2004 |
| 6738948 | Iteration terminating using quality index criteria of turbo codes A method of terminating iteration calculations in the decoding of a received convolutionally coded signal includes a first step of providing a turbo decoder with a first and second recursion processors connected in an iterative loop. Each processor has an associated... | 05/18/2004 |
| 6735731 | Architecture for built-in self-test of parallel optical transceivers Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator and a clock divider circuit connected to provide a h... | 05/11/2004 |
| 6728912 | SOI cell stability test method A method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, uses a reset test circuit with a wordline pulse width control circuit which can be implemented without performance impact and allows using unused silicon to minimize area usag... | 04/27/2004 |
| 6728930 | Method for computing the internet checksum The present invention is directed to a method of updating a checksum associated with a packet of information to be transferred between correspondents. The method comprises the steps of: changing the value of a field; computing a complement; computing a difference; c... | 04/27/2004 |
| 6728928 | Modified viterbi detector for jitter noise dominant channels A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to λk(i)=(zk−yk(i))2−α(i), wherein α(i) | 04/27/2004 |
| 6728913 | Data recycling in memory A method of programming a memory device having a plurality of pages of memory. The method includes programming the memory, monitoring the memory for defects, creating a copy of the data, erasing the old version of the data, and rewriting the data. The first page of ... | 04/27/2004 |
| 6728926 | Encoding rate detection method and encoding rate detection device In accordance with a rate detecting method for detecting a predetermined rate at which a received signal has been coded, the coded signal is decoded based on a first synchronizing signal having a frequency corresponding to a first rate such that a first decoded sign... | 04/27/2004 |
| 6725417 | Sequential decoding apparatus and method Sequentially decoding a plurality of symbol sets of an incoming data sequence with less amount of computation in an application wherein paths in a code tree do not occur equiprobably is disclosed. A code tree is previously memorized which comprises a plurality of pa... | 04/20/2004 |
