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| Number | Title | Issue Date |
| 8169233 | Programming of DIMM termination resistance values Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the p... | 05/01/2012 |
| 8159265 | Memory for metal configurable integrated circuits Memory for a semiconductor device is disclosed. The memory array comprises: a memory cell replicated in rows and columns to form an array; and a plurality of first horizontal decode signals, each horizontal signal common to all the memory cells in a said row; and a ... | 04/17/2012 |
| 8130010 | Signal lines with internal and external termination Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impeda... | 03/06/2012 |
| 8125243 | Integrity checking of configurable data of programmable device Methods and a system for continuous integrity checking of configuration data of programmable device are disclosed. In one embodiment, a method includes performing a redundancy check (RC) of configuration data loaded to configuration registers to produce a master RC ... | 02/28/2012 |
| 8111006 | Light emitting diode driving apparatus A light emitting diode driving apparatus 10 of the present invention includes: a driving voltage generating section 11 for generating a driving voltage Vout of an LED; a driving current control section 12 for PWM controlling driving currents iW | 02/07/2012 |
| 8098084 | Transmission apparatus for differential communication A transmission apparatus for differential communication includes a driver bridge circuit and a pair of noise protection circuits. The driver bridge circuit includes four output devices that are independently connected between each of a pair of transmission lines and... | 01/17/2012 |
| 8076957 | Semiconductor integrated circuit The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a thir... | 12/13/2011 |
| 8067970 | Multi-write memory circuit with a data input and a clock input Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those poi... | 11/29/2011 |
| 8067959 | Programmable delay line compensated for process, voltage, and temperature A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-d... | 11/29/2011 |
| 8063674 | Multiple supply-voltage power-up/down detectors A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the c... | 11/22/2011 |
| 8063657 | Systems and devices for quantum processor architectures A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The archit... | 11/22/2011 |
| 8053997 | Load control device having a trigger circuit characterized by a variable voltage threshold A two-wire load control device, such as a dimmer, is operable to control the amount of power delivered to an electrical load, such as a magnetic low-voltage (MLV) load, and comprises a bidirectional semiconductor switch, a timing circuit, a trigger circuit having a ... | 11/08/2011 |
| 8054102 | Interface device and interface system An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits... | 11/08/2011 |
| 8050651 | Detector, RF circuit with detector, and mobile device with RF circuit The detector is reduced in DC power consumption when an input signal is at a low amplitude level. The detector includes first and second input terminals, first and second transistors, and a load element. The first and second input terminals are supplied with complem... | 11/01/2011 |
| 8044680 | Semiconductor memory device and on-die termination circuit An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a... | 10/25/2011 |
| 8044685 | Floating driving circuit A floating driving circuit according to the present invention comprises an input circuit to receive an input signal. A latch circuit receives a trigger signal for generating a latch signal. The latch signal is used to turn on/off a switch. A coupling capacitor is co... | 10/25/2011 |
| 8044684 | Input and output buffer including a dynamic driver reference generator A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dyn... | 10/25/2011 |
| 8044682 | FPGA having low power, fast carry chain An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are ... | 10/25/2011 |
| 8044681 | Apparatus and method for channel-specific configuration in a readout ASIC An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration ... | 10/25/2011 |
| 8044679 | On-die termination control circuit of semiconductor memory device On-die termination control circuit of semiconductor memory device includes a counter configured to count an external clock to output a first code, and to count an internal clock to output a second code, a transfer controller configured to determine whether to transf... | 10/25/2011 |
| 8040078 | LED dimming circuit A LED dimming circuit is provided. The LED dimming circuit has an LED driver, an LED dimmer, and at least one LED light source. A resistor is connected between a dimming control output of the LED dimmer and dimming control input of the LED dimmer. The LED dimming ci... | 10/18/2011 |
| 8040150 | Impedance adjustment circuit An impedance adjustment circuit according to the present invention includes a first input buffer which detects that an input signal exceeds VREFA, a second input buffer which detects that the input signal exceeds VREFB, VREFB being higher than VREFA, a counter circu... | 10/18/2011 |
| 8040151 | Programmable logic device with programmable wakeup pins A programmable logic device (PLD) adapted to enter a low-power or sleep mode with programmable wakeup pins in a wakeup group of pins is disclosed. Wake on a single pin change, wake on vector, and wake on a single pin transition are supported. The approach is to sele... | 10/18/2011 |
| 8035420 | Semiconductor device and method for operating the same A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to ampli... | 10/11/2011 |
| 8035415 | Shift register and semiconductor display device The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The... | 10/11/2011 |
| 8035414 | Asynchronous logic automata A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements p... | 10/11/2011 |
| 8035413 | Dynamic impedance control for input/output buffers A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode... | 10/11/2011 |
| 8035568 | Electromagnetic reactive edge treatment An electromagnetic reactive edge treatment including an array of capacitively-loaded loops is disposed at or near an edge of a conductive wedge. The axes of the loops are oriented parallel to the edge of the wedge. This edge treatment may enhance or suppress the har... | 10/11/2011 |
| 8030963 | Integrated circuit and standard cell for an integrated circuit In one embodiment, a cell of an integrated circuit includes a master-slave flip-flop and comparator logic having inputs adapted to receive an input signal of the master-slave flip-flop, an inverted input signal of the master-slave flip-flop, an output signal of the ... | 10/04/2011 |
| 8030960 | Converting dynamic repeaters to conventional repeaters A method for converting a repeater circuit from a dynamic repeater circuit to a static repeater circuit. The method includes disconnecting a feedback path coupled to a first stage of the dynamic repeater circuit and electrically shorting gate terminals of first and ... | 10/04/2011 |
| 8030962 | Configuration random access memory Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the in... | 10/04/2011 |
| 8030971 | High-density logic techniques with reduced-stack multi-gate field effect transistors Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required ... | 10/04/2011 |
| 8030970 | Device forming a logic gate for detecting a logic error The invention relates to a device for forming an electric circuit comprising logic means (30) generating and using small signals of intermediate levels between the device supply levels and means for detecting signals leaving the small signal range. ... | 10/04/2011 |
| 8030968 | Staged predriver for high speed differential transmitter According to various embodiments, a differential transmitter includes a driver and a predriver. In various embodiments, the predriver may include pull-up transistors and pull-down transistors configured in various ways to produce a staged output signal during a pull... | 10/04/2011 |
| 8030967 | Method and apparatus involving a receiver with a selectable performance characteristic A circuit has a programmable mode control section, and a receiver section with first and second input terminals and an output terminal. The method and apparatus involve setting the mode control section to one of first and second states in response to user input, and... | 10/04/2011 |
| 8026838 | Current mode analog-to-digital converter A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the... | 09/27/2011 |
| 8026737 | Fusing apparatus for correcting process variation An fusing apparatus for correcting process variation is provided. The fusing apparatus for correcting the process variation of the semiconductor device includes a fusing part including a fusing resistor fused by a current penetrating; a current driving transistor fo... | 09/27/2011 |
| 8022724 | Method and integrated circuit for secure reconfiguration of programmable logic Approaches for secure configuration of a programmable logic integrated circuit (IC). In one approach, a method includes programming configuration memory of the programmable logic IC with a first configuration bitstream. At least a portion of a second configuration b... | 09/20/2011 |
| 8022730 | Driving circuit with slew-rate enhancement circuit A driving auxiliary circuit receiving an input voltage to control an output voltage of an operational amplifier via a first switch and a second switch is provided. A pull-low circuit turns on the first switch, including a first input terminal coupled to a high volta... | 09/20/2011 |
| 8022729 | Signal driver circuit having adjustable output voltage for a high logic level output signal A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having ... | 09/20/2011 |
