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| Number | Title | Issue Date |
| 8185676 | Transitions between ordered and ad hoc I/O request queueing Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The... | 05/22/2012 |
| 8166207 | Querying a device for information In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write requ... | 04/24/2012 |
| 8156258 | Recording and replaying device A recording and replaying device is provided in which a user can easily diagnose failure when a built-in storage device of the device fails. In a normal operation state, a microcomputer controls a signal path switching mechanism to connect a signal processing device... | 04/10/2012 |
| 8156263 | Information processing apparatus and storage device control method An information processing apparatus includes: a processor configured to run an operating system; a plurality of storage devices connected to the processor; a detection module configured to detect a boot process for installing the operating system; a determination mo... | 04/10/2012 |
| 8140715 | Virtual media input device A virtual media device is described for processing one or more input signals from one or more physical media input devices, to thereby generate an output signal for use by a consuming application module. The consuming application module interacts with the virtual me... | 03/20/2012 |
| 8135885 | Data packer for packing and aligning write data A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower ba... | 03/13/2012 |
| 8131889 | Command queue for peripheral component In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral compon... | 03/06/2012 |
| 8073991 | Isolated HART interface with programmable data flow An isolated highway addressable remote transfer (HART) interface with programmable data flow is provided. The isolated HART interface includes a HART channel having at least one pair of terminals configured to connect with a HART device via a current loop. The HART ... | 12/06/2011 |
| 8069285 | Methods and systems for improving communication throughput of storage links Methods and systems for improving communication throughput of a link between SAS/SATA devices. The link, initially established at a first signal rate, is one of a SATA link and a SAS link. A SAS/SATA device increments one of the at least one counter based on an erro... | 11/29/2011 |
| 8069274 | System and method for serial data communications between host and communications devices, and communications device employed in the system and method A communications device includes a communications circuit, a memory, an identifier generator, and a latency controller. The communications circuit exchanges serial data with a host computer and a downstream device, and includes a first input, a first output, a secon... | 11/29/2011 |
| 8069284 | Semiconductor memory device, memory system and data recovery methods thereof A semiconductor memory device includes a nonvolatile memory device having a plurality of physical sectors, and a memory controller configured to translate a logical address received from a host to a physical address, with reference to mapping data that defines a cor... | 11/29/2011 |
| 8060667 | Apparatus and method for processing high speed data using hybrid DMA An apparatus and a method for processing high speed data using hybrid Direct Memory Access (DMA) are provided. The method includes determining a size of data to be transmitted, determining a memory access method of the data by comparing the determined size of the da... | 11/15/2011 |
| 8060663 | Physical layer interface for computing devices A physical layer device for interfacing with multiple computing devices includes a digital core and first and second analog front ends. The digital core is operative to perform one or more functions of the physical layer device. Each of the first and second analog f... | 11/15/2011 |
| 8055816 | Memory controllers, memory systems, solid state drives and methods for processing a number of commands The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command que... | 11/08/2011 |
| 8046501 | Vehicle control and interconnection system An integrated system to control peripherals in a vehicle includes a control and interconnection system having a supervisory processor and/or supervisory control. The control and interconnection system is responsive to feedback from peripherals associated with the ve... | 10/25/2011 |
| 8041856 | Skip based control logic for first in first out buffer A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, ... | 10/18/2011 |
| 8037217 | Direct memory access in a hybrid computing environment DMA in a computing environment that includes several computers and DMA engines, the computers adapted to one another for data communications by an data communications fabric, each computer executing an application, where DMA includes: pinning, by a first application... | 10/11/2011 |
| 8037212 | Event notification system and method A technique for user notification involves modifying a title associated with a process to include information about an event that calls for user notification. A method according to the technique may include running a process, processing an event, generating a string... | 10/11/2011 |
| 8024496 | Enhanced memory migration descriptor format and method An enhanced migration descriptor migrates a plurality of source sub-pages in a large source page accessible by direct memory access devices. A splitter and selector are integrated into a configuration of a computer. Responsive to a request to migrate a large page co... | 09/20/2011 |
| 8024498 | Transitions between ordered and ad hoc I/O request queueing Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The... | 09/20/2011 |
| 8024491 | Detecting a connection to an unpowered host A method and apparatus for detecting a connection between a peripheral device and a host device is described. ... | 09/20/2011 |
| 8019921 | Intelligent memory buffer A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes... | 09/13/2011 |
| 8015328 | Information storage device, information processing system, and setting method of data transfer mode of information processing device An information storage device includes a storage that stores transfer data from an information processing device, the information storage device being removably connected to the information processing device, a switch unit that switches a data transfer mode of the i... | 09/06/2011 |
| 8010718 | Direct memory access in a hybrid computing environment Direct memory access (‘DMA’) in a hybrid computing environment that includes a host computer, an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where DMA includes identi... | 08/30/2011 |
| 8010711 | Universal multimedia A memory device removably insertable into or otherwise removably connected to a plurality of host devices includes a first memory storing multimedia data. A first circuit portion of the memory device determines the host device capabilities when the memory device is ... | 08/30/2011 |
| 8010713 | Storage system, storage apparatus, and method for hot swapping of firmware A storage system includes a host and a storage apparatus. The host having multiple paths connecting with the storage apparatus transfers path identification information received from the storage apparatus, to the storage apparatus via all paths other than a path thr... | 08/30/2011 |
| 8006004 | Non-intrusive debug port interface A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least on... | 08/23/2011 |
| 8001289 | Digital audio/video apparatus and method that can perform additional operations An audio/video (AV) apparatus such as a digital television set and a digital set-top-box device, which can perform additional operations such as an electronic album, MP3 and FIMS, and an additional operation performing apparatus appropriate for the digital AV appara... | 08/16/2011 |
| 8001290 | Vehicle computer system with audio entertainment system A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits ... | 08/16/2011 |
| 8001292 | Data transfer controlling device and IC card A data transfer controlling device is mounted in an IC card having: a communication device for data communication with an external device; a memory device for storing data received from and transmitted to the external device; and an operation processing device for c... | 08/16/2011 |
| 8001286 | Multipurpose and programmable pad for an integrated circuit A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple differ... | 08/16/2011 |
| 8001294 | Methods and apparatus for providing a compressed network in a multi-processing system The present invention provides methods and apparatus for transferring and storing data among processors and memory in a multiprocessor system. The data is compressed locally before it is sent to a shared memory. The memory stores the data in its compressed state, bu... | 08/16/2011 |
| 7991922 | System on a chip for networking A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more n... | 08/02/2011 |
| 7991921 | System and method for reducing power consumption of memory in an I/O controller A memory system for an I/O controller which includes a memory with multiple memory blocks, a supply voltage control circuit providing power to each memory block, and control logic. Each memory block retains stored information with reduced power consumption when rece... | 08/02/2011 |
| 7987301 | DMA controller executing multiple transactions at non-contiguous system locations A direct memory access controller comprises a plurality of registers defining parameters for multiple direct memory access transactions and transfer control circuitry responsive to data in the plurality of registers. The transfer control circuitry is adapted to auto... | 07/26/2011 |
| 7979608 | Lane to lane deskewing via non-data symbol processing for a serial point to point link Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the n... | 07/12/2011 |
| 7979589 | Method, apparatus, and system for port multiplier enhancement A method, apparatus and system are provided for enhancing port multipliers. In one embodiment, a port multiplier is configured to couple a network host with port multipliers. The port multiplier includes a top port multiplier to establish and maintain communication ... | 07/12/2011 |
| 7979599 | Method for the allocation of memory in a buffer memory A method for allocation of a buffer memory with three buffers of a module having a processing unit and a bus connection is provided. The module sends or receives data via the bus connection and uses the processing unit to generate data for transmission via the bus c... | 07/12/2011 |
| 7979612 | Communication method and apparatus A communication method allows a host to access and send commands to an apparatus across a network or communication system by encoding data as a sequence of status signals and sending the data from the host on a communication channel between the host and an auxiliary... | 07/12/2011 |
| 7975081 | Image display system and control method therefor Provided are an image display system and a control method for the image display system capable of displaying an image, which is represented by raster image data to be transferred through burst transmission and which is formed with a plurality of scanning lines, thro... | 07/05/2011 |
