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| Number | Title | Issue Date |
| 8185805 | Network communication protocol for large scale distribution of streaming content Forward error correction may be implemented in a network having first, second, third and fourth nodes. The second node receives streaming media message packets and one or more check packets from an upstream first node. The second node transmits the message packets a... | 05/22/2012 |
| 8185799 | Transmitting/receiving system and method of processing broadcast signal in transmitting/receiving system A receiving system and a method of processing data are disclosed herein. The receiving system includes a receiving unit, an equalizer, a block decoder, and an RS frame decoder. The receiving unit receives and demodulates a broadcast signal. Herein, the broadcast sig... | 05/22/2012 |
| 8185798 | Techniques for reducing joint detection complexity in a channel-coded multiple-input multiple-output communication system A technique for joint detection of channel-coded signals in a multiple-input multiple-output system includes detecting, when a decoded signal associated with a first symbol stream passes a cyclic redundancy check, channel-coded signals in the first symbol stream and... | 05/22/2012 |
| 8181101 | Data bus system, its encoder/decoder and encoding/decoding method The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data accor... | 05/15/2012 |
| 8181086 | Memory array error correction apparatus, systems, and methods Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array... | 05/15/2012 |
| 8181076 | Method for retransmitting a data sequence according to channel condition in a wireless communications network Retransmitting a data sequence over a wireless network according to channel conditions proceeds by transmitting a first transmitting signal representing the data using a first set of beamforming weighting vectors generated according to a first channel condition. A r... | 05/15/2012 |
| 8171364 | System and method for power outage and restoration notification in an advanced metering infrastructure network A method and system are provided to transmit a meter power status. The method includes recognizing a power status change at a meter. The method includes, if the meter is scheduled to transmit first, transmitting a notification message to at least one neighboring met... | 05/01/2012 |
| 8166380 | Method and apparatus for identifying paths having appropriate lengths for fault simulation A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element t... | 04/24/2012 |
| 8161344 | Circuits and methods for error coding data blocks A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to c... | 04/17/2012 |
| 8161350 | Method and system for encoding a data sequence A communication method and a communication system including a first entity (3) including an information source (9) and a coder device (11) connected by a channel (7) transmitting data to a second entity (5) including a decoder devi... | 04/17/2012 |
| 8161361 | Averaging signals to improve signal interpretation Systems and techniques to interpret signals on a noisy channel. In general, in one implementation, the technique includes: interpreting an input signal as discrete values, and in response to an inadequate signal, averaging multiple signals to improve interpretation ... | 04/17/2012 |
| 8161343 | Nibble encoding for improved reliability of non-volatile memory A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in which the initial nibble value is Fh and on program operations that result in a nibble value of 0h. The no... | 04/17/2012 |
| 8161365 | Cyclic redundancy check generator A cyclic redundancy check (“CRC”) generator and method therefor are described. Checksum bits and checksum enable bits are bitwise ANDed to provide interim checksum outputs. The interim checksum outputs are XORed to provide resultant checksum outputs. Data bits a... | 04/17/2012 |
| 8156410 | Fast debugging tool for CRC insertion in MPEG-2 video decoder A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an inp... | 04/10/2012 |
| 8156398 | Parameter estimation based on error correction code parity check equations A method for operating a memory, which includes analog memory cells, includes encoding data with an Error Correction Code (ECC) that is representable by a plurality of equations. The encoded data is stored in a group of the analog memory cells by writing respective ... | 04/10/2012 |
| 8156409 | Selectively applied hybrid min-sum approximation for constraint node updates of LDPC decoders In accordance with one or more embodiments, a decoder may determine whether a lowest reliability value of a plurality of codeword bits that correspond to a particular output reliability value for a particular constraint node of a parity-check matrix is greater than ... | 04/10/2012 |
| 8151167 | Program processing device and program processing method A program processing device has a non-volatile storage, a volatile storage and a controller. The controller has a detector that detects a bit flip in the program, the variable data, and the constant data in the volatile storage, a constant recovery unit that, when t... | 04/03/2012 |
| 8151164 | Method and apparatus for encoding and decoding high speed shared control channel A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive unit (WTRU) identity (ID) and a generator matrix with a maximum minim... | 04/03/2012 |
| 8151158 | Method and system for decoding a data burst in a communication system The present invention provides methods and systems for decoding a data burst in a communication system. A data burst, including a plurality of forward error correction (FEC) blocks, is received. At least one FEC block of the data burst is decoded. Thereafter, it is ... | 04/03/2012 |
| 8145982 | Method and system for redundancy-based decoding of voice content in a wireless LAN system Aspects of a method and system for redundancy-based decoding of voice content in a wireless local area network (WLAN) system are provided. A WLAN receiver may determine whether a decoded portion of a received packet comprises voice content and may select a redundanc... | 03/27/2012 |
| 8140939 | Flash error correction A data processing device for detecting and correcting data errors of a re-writable memory via an error correction algorithm. In one embodiment, the data processing device includes a coding unit implemented in hardware and an error correction unit implemented in soft... | 03/20/2012 |
| 8140951 | Method and system for instruction address parity comparison A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing ci... | 03/20/2012 |
| 8136018 | Network communication protocol for large scale distribution of streaming content Forward error correction may be implemented in a network having first, second and third nodes. The second node receives streaming media message packets and one or more check packets from an upstream first node. The second node transmits the message packets and check... | 03/13/2012 |
| 8136023 | Decoding method for tail-biting convolutional codes using a search depth viterbi algorithm A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states a... | 03/13/2012 |
| 8136007 | Adaptive error correction A system and method for adaptive error correction that optimizes bandwidth by taking into account expected, or predicted, interferences. The bandwidth used for error correction is applied judiciously based on the value of the content and the need to receive the cont... | 03/13/2012 |
| 8132079 | Radio communication apparatus A radio communication apparatus is provided in Protocol Data Unit (PDU) transmission, in which the tail end (boundary) of a packet is detected based on the calculation result of an error detection calculation (Frame Check Sequence (FCS) calculation), without use of ... | 03/06/2012 |
| 8127197 | Method and apparatus for radio link control padding for enhanced general packet radio service A method (300) for radio link control padding is shown. In its simplest form, it can include the steps of: providing (310) N bytes of data from a base station; interleaving (320) the N bytes of data using a turbo-interleaver; pre-pending (330... | 02/28/2012 |
| 8127215 | Signal loss detector for high-speed serial interface of a programmable logic device A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transition... | 02/28/2012 |
| 8122317 | Two-dimensional parity technique to facilitate error detection and correction in memory arrays The present invention is directed to a two-dimensional parity technique for data to be stored in one or more memory arrays, each of which has various rows and columns of cells. A row of bits in a super bundle is referred to as a row bundle. A super bundle includes n... | 02/21/2012 |
| 8122319 | Page-based failure management for flash memory A page-based failure management system for flash memory includes at least one flash memory device which includes at least one page and at least one operable page. The system also includes an indication of operability of the at least one page in the at least one flas... | 02/21/2012 |
| 8117522 | Sphere decoder and decoding method thereof A sphere decoder sets a Euclidean distance between a lattice vector obtained by using an MMSE or ZF estimate and a received signal as an initial radius, further reduces the initial radius, and searches lattices points included inside a hypersphere with the further r... | 02/14/2012 |
| 8117525 | Method for parallel data integrity checking of PCI express devices An apparatus and method for supporting PCI Express is disclosed. A physical layer has a PCI Express interface for receiving data from a PCI Express compatible communication medium. The data is in the form of a packet. A data link layer is disclosed for verifying a C... | 02/14/2012 |
| 8117526 | Apparatus and method for generating a transmit signal and apparatus and method for extracting an original message from a received signal A method for extracting an original message from a received signal including data bits representing the original message or an inverted version thereof, an indicator indicating whether the data bits represent the original message or the inverted version thereof, and... | 02/14/2012 |
| 8108752 | Error correcting device, method, and program A device, method, and program are provided to prevent an increase of the probability of erroneous correction for a burst error having a length exceeding detection capability even if high correction capability is selected for a random error. In one embodiment, an app... | 01/31/2012 |
| 8108749 | Diversity combining iterative decoder An iterative decoder circuit includes an N number of sub-decoders, N−1 of the sub-decoders each being responsive to a baseband signal from one of M number of signal processing circuits. Each of the N−1 number of sub-decoders includes, an inner delay responsive t... | 01/31/2012 |
| 8099644 | Encoders and methods for encoding digital data with low-density parity check matrix A method for encoding digital data with a low-density parity check (LDPC) matrix includes: indirectly storing a non-regular portion of the LDPC matrix by storing a plurality of indices corresponding to a plurality of non-zero sub-matrices of the non-regular portion,... | 01/17/2012 |
| 8099646 | Low density parity check (LDPC) code Low density parity check code (LDPC) base parity check matrices and the method for use thereof in communication systems. The method of expanding the base check parity matrix is described. Examples of expanded LDPC codes with different code lengths and expansion fact... | 01/17/2012 |
| 8078935 | Method and system for encoding and decoding information with modulation constraints and error control A method and system for encoding a segment of user data words into a segment of code words so that both modulation constraints and a predetermined parity-check constraint are satisfied. Each segment of the user data is partitioned into several data words, and encode... | 12/13/2011 |
| 8078930 | Methods and apparatus for modifying a backup data stream including logical partitions of data blocks to be provided to a fixed position delta reduction backup application In accordance with one embodiment, a backup data stream is modified to be provided to a fixed position delta reduction backup method. When a data stream is received, the data stream may be parsed into a plurality of logical components, where each of the logical comp... | 12/13/2011 |
| 8078933 | Decoder for low-density parity-check convolutional codes Decoder for low-density parity check convolutional codes. In at least some embodiments, a decoder (200) for arbitrary length blocks of low-density, parity-check codes includes a plurality of interconnected processors (202), which further include a plur... | 12/13/2011 |
