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| Number | Title | Issue Date |
| 6256743 | Selective power-down for high performance CPU/system A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and d... | 07/03/2001 |
| 6219741 | Transactions supporting interrupt destination redirection and level triggered interrupt semantics In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data rep... | 04/17/2001 |
| 6199133 | Management communication bus for networking devices A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at least one slave device, where the bus master and slave devices are distributed within the netw... | 03/06/2001 |
| 6195724 | Methods and apparatus for prioritization of access to external devices According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of reqeusting device requests of the external devices, a request queue controller unit coupled to t... | 02/27/2001 |
| 6185688 | Method for controlling security of a computer removably coupled in a network A method for controlling physical security of a computer removably coupled to a network wherein a security administrator associated with a server invokes a timer in a client computer and disables the client computer if the computer is not operated within ... | 02/06/2001 |
| 6182121 | Method and apparatus for a physical storage architecture having an improved information storage and retrieval system for a shared file environment A distributed storage system provides a method and apparatus for storing, retrieving, and sharing data items across multiple physical storage devices that may not always be connected with one another. The present invention comprises one or more `partition... | 01/30/2001 |
| 6178477 | Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource The present invention comprises a system for implementing pseudo delayed transactions through a bridge in order to guarantee access to a shared device. The system of the present invention functions in a computer system having a plurality of busses, includ... | 01/23/2001 |
| 6170029 | Voltage overshoot control in hot plug system A method and implementing computer system is provided in which PCI bus load conditions are detected and dummy loads are selectively switched into the PCI bus under light load conditions in order to avoid voltage overshoot problems. Load control logic rece... | 01/02/2001 |
| 6170032 | Priority encoder circuit A priority encoder circuit (10, 60) is provided. The priority encoder circuit (10, 60) includes a plurality of inputs (38, 90) and outputs (40, 92). The number of inputs (38, 90) equals the number of outputs (40, 92), and each input (38, 90) corresponds t... | 01/02/2001 |
| 6170025 | Distributed computer system supporting remote interrupts and lock mechanism A distributed computer system includes a host CPU, a network/host bridge, a network/I/O bridge and one or more I/O devices. The host CPU can generate a locked host transaction, which is wrapped in a packet and transmitted over a network to the remote I/O ... | 01/02/2001 |
| 6163827 | Method and apparatus for round-robin flash channel arbitration Round-robin arbitration circuit selects in clock cycle channel contending for arbitration; each arbitrated channel having channel number in sequence of channel numbers. Channel is designated as currently arbitrated; designated channel having designated nu... | 12/19/2000 |
| 6163823 | Dynamic addressing of devices on a shared medium network with a keyline A system for assigning unique addresses to a series of electronic units in an in-flight entertainment system. The electronic units are connected via an interconnect bus and a keyline wire. During initialization of the system, each electronic unit is enabl... | 12/19/2000 |
| 6163846 | Method and circuit for backing up memory and calender Disclosed is a method far backing up memory and calendar, which has the steps of: providing a back-up power source for the calendar separated from the back-up power source for both the memory and the calendar; and continuing to back up the calendar by the... | 12/19/2000 |
| 6161187 | Skipping clock interrupts during system inactivity to reduce power consumption A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capab... | 12/12/2000 |
| 6157976 | PCI-PCI bridge and PCI-bus audio accelerator integrated circuit A semiconductor device with an embedded PCI 2.1 compliant bridge provides expanded functionality as system-level implementations of a PCI-to-PCI bridge, and enhances the level of integration possible. The embedded PCI-to-PCI bridge allows the creation of ... | 12/05/2000 |
| 6148352 | Scalable modular data storage system A storage system is provided for storing data for a computer system where the storage capacity can be incrementally increased without disrupting the operations of the storage system. The storage system comprises a base unit, and a plurality of modular uni... | 11/14/2000 |
| 6141715 | Method and system for avoiding live lock conditions on a computer bus by insuring that the first retired bus master is the first to resubmit its retried transaction A computer system avoids livelock conditions on a computer bus coupled to plural bus masters. In response to receiving a transaction request from a first bus master across the computer bus, a bus controller transmits a retry command to the first bus maste... | 10/31/2000 |
| 6134604 | Communication apparatus for communicating with a plurality of communication control units cascade-connected A communicating apparatus for performing a serial communication with a plurality of communication control units which are cascade connected, including a communicating unit for performing a serial communication with each of the communication control units,... | 10/17/2000 |
| 6134623 | Method and system for taking advantage of a pre-stage of data between a host processor and a memory system A system for coupling a host processor to a memory subsystem and enabling efficient transfer of data therebetween, where the memory subsystem responds to a data block read request by dispatching the designated data block and N data segments that are used ... | 10/17/2000 |
| 6134622 | Dual mode bus bridge for computer system A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently ... | 10/17/2000 |
| 6125450 | Stop clock throttling in a computer processor through disabling bus masters Microprocessors are often used in portable equipment that run on battery power. Thus, microprocessors used in such environments should save power when ever possible. Processors that have internal cache memories and allow external bus masters present a dif... | 09/26/2000 |
| 6122747 | Intelligent subsystem interface for modular hardware system A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and ... | 09/19/2000 |
| 6122444 | Method and apparatus for manipulation of digital data in multiple parallel but incongruent buffers A method and apparatus for performing signal processing using incongruent buffers. According to one method described, a maximum concurrent run length (MCRL) is calculated to indicate the maximum run length before any of a plurality of buffers is exhausted... | 09/19/2000 |
| 6115748 | Prioritized access to shared buffers In a link-level flow controlled system, a method and apparatus providing the ability to partition a buffer resource among multiple prioritized buffer subsets through definition of at least one threshold, the buffer resource being shared by a plurality of ... | 09/05/2000 |
| 6115764 | Acyclic cable bus having redundant path access A novel PHY concentrator design is disclosed. The PHY concentrator provides switchable dual paths to disk drives from dual controllers. The concentrator uses a common input that is shifted into an internal shift register during the bus reset state and use... | 09/05/2000 |
| 6112273 | Method and apparatus for handling system management interrupts (SMI) as well as, ordinary interrupts of peripherals such as PCMCIA cards An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. Th... | 08/29/2000 |
| 6108741 | Ordering transactions A computer system includes a first device on a first data bus, a second device on a second data bus, and a bridge device that delivers data transactions between the two devices. The bridge device includes an execution queue that stores only a higher prior... | 08/22/2000 |
| 6105099 | Method for synchronizing use of dual and solo locking for two competing processors responsive to membership changes To satisfy host requests, two competing processors self-manage access to a shared resource. Each processor maintains a lock table listing that processor's access state regarding the shared resource. Each processor repeatedly sends the other processor a st... | 08/15/2000 |
| 6094725 | Magnetic disk apparatus A magnetic disk apparatus includes at least two systems, each system having at least one power unit and at least one battery unit ancillary to the power unit. The disk apparatus also includes at least one common power unit having a pluralities of batterie... | 07/25/2000 |
| 6092205 | Device for automatically locking a power button in a computer A device for automatically locking a power button in a computer is to prevent a power button from operating by someone when the user uses a mouse. The device has a power button blocking part 100 installed between a power button 420, which moves forward an... | 07/18/2000 |
| 6088754 | Generic serial interface with automatic reconfigurability A generic serial interface includes any one of multiple transition cables having a first connector conforming to one of several different serial interface standards. A second generic connector is connected to a second end of the transition cables. A confi... | 07/11/2000 |
| 6079022 | Method and apparatus for dynamically adjusting the clock speed of a bus depending on bus activity A dynamic clock control comprising an idle detector and a variable speed clock supply. The idle detector detects when an idle condition appears on the bus and sends an appropriate control signal to the variable speed clock supply. The clock supply, which ... | 06/20/2000 |
| 6067590 | Data bus agent including a storage medium between a data bus and the bus agent device A system and method of transferring data on a data bus is disclosed. The system includes a data bus agent having a storage medium connectable to a data bus and arranged to store data and a bus agent device adapted to receive data from the storage medium. ... | 05/23/2000 |
| 6067594 | High frequency bus system A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or... | 05/23/2000 |
| 6067588 | Channel interface signal tracing input/output controller apparatus An input/output controller apparatus has a CPU arranged for directing an FPGA to generate a desired trace logic circuit and a channel controller to start communication with a host system. The channel controller while performing the communication with the ... | 05/23/2000 |
| 6058448 | Circuit for preventing bus contention A circuit for controlling the data transmissions among two devices capable transmitting information, via an output buffer, over a bus, so as to prevent bus contention, is comprised of a first device enabled circuit for generating a first device enabled si... | 05/02/2000 |
| 6047348 | System and method for supporting a multiple width memory subsystem The present invention provides a memory system interface design, which provides access to a dual width memory bus. Specifically, a subsystem and method provides for interfacing with a 32 bit or a 64 bit bus. The 32 bit bus would be used for low end produc... | 04/04/2000 |
| 6044473 | Portable computer having a switch for changing a power-controlling mode The present invention relates to a portable computer having a switch for changing a power-controlling mode. In a portable computer which a display and a main housing are connected by a hinge, the object of the present invention cuts off or controls power ... | 03/28/2000 |
| 6038613 | Prefetching and storing device work information from multiple data storage devices A device controller is described within a data storage system for pre-fetching device work information from multiple data storage devices, and accumulating the device work information to immediately respond to a subsequent device poll command from a stora... | 03/14/2000 |
| 6038688 | Node disjoint path forming method for hypercube having damaged node A node disjoint path forming method for a hypercube having a damaged node which is capable of using unused nodes (surplus nodes) in an n-number of node disjoint paths each having a length of n with respect to n-dimensional hypercubes more than 4-cube, so ... | 03/14/2000 |
