U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

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Patent No. 6725510

Inclining coffin

A coffin, for allowing inclination for display of a deceased person in a natural position.

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Examiner: Chung, Phung M.


Primary examiner statistics: 736 patents; average approval time: 736 days
Assistant examiner statistics: 280 patents; average approval time: 912 days

Patents as Primary Examiner (view all)

Patent No. Patent Title:
7669093 Information radio transmission system
7650546 Flexible JTAG architecture
7464307 High performance serial bus testing methodology
7464306 Status of overall health of nonvolatile memory
7457998 Scan register and methods of using the same
7457999 Debug port system for control and observation
7454670 Data management apparatus and method of flash memory
7451383 Rate matching device and method for a data communication system
7451373 Circuit for compression and storage of circuit diagnosis data
7447952 Method of and apparatus for managing disc defects using temporary...
7447951 Information storage medium, method of managing replacement inform...
7447959 Semiconductor integrated circuit and a method of testing the same
7447967 MIMO hybrid-ARQ using basis hopping
7444561 Verifier for remotely verifying integrity of memory and method th...
7444580 System and method for interleaving data in a communication device
7444575 Architecture and method for testing of an integrated circuit devi...
7444566 Memory device fail summary data reduction for improved redundancy...
7444559 Generation of memory test patterns for DLL calibration
7441166 Testing apparatus and testing method
7437624 Method and apparatus for analyzing serial data streams
7437653 Erased sector detection mechanisms
7434116 Unitary testing apparatus for performing bit error rate measureme...
7434122 Flash memory device for performing bad block management and metho...
7434119 Method and apparatus for memory self testing
7434113 Method of analyzing serial data streams
7428673 Test method for determining the wire configuration for circuit ca...
7428670 Apparatus for managing disc defects using temporary defect manage...
7428676 Boundary scan device
7424657 Method and device for testing an integrated circuit, integrated c...
7424652 Method and apparatus for detection of transmission unit loss and/...
7421631 Semiconductor device with termination resistor circuit
7418640 Dynamically reconfigurable shared scan-in test architecture
7418642 Built-in-self-test using embedded memory and processor in an appl...
7409615 Test apparatus and test method
7409618 Self verifying communications testing
7409631 Error-detection flip-flop
7409620 Simplified high speed test system
7406641 Selective control of test-access ports in integrated circuits
7401272 Apparatus and method for high speed sampling or testing of data s...
7401276 Semiconductor device with test circuit and test method of the sam...

Patents as Assistant Examiner (view all)

Patent No. Patent Title:
6363358 Integrated hangtag production system
6360210 Method and system for enabling smaller investors to manage risk i...
6226619 Method and system for preventing counterfeiting of high price who...
6212504 Self-authentication of value documents using encoded indices
6169976 Method and apparatus for regulating the use of licensed products
6167385 Supply chain financing system and method
6161095 Treatment regimen compliance and efficacy with feedback
6157920 Executable digital cash for electronic commerce
5878209 Apparatus and method for identifying a failed subscriber unit in ...
5659682 Scheme to determine completion of directory operations for server...
5638379 Encoding system for distribution of synchronization
5638510 Multiplexed system with watch dog timers
5636224 Method and apparatus for interleave/de-interleave addressing in d...
5629943 Integrated circuit memory with double bitline low special test mo...
5630050 Method and system for capturing and controlling access to informa...
5627838 Automatic test circuitry with non-volatile status write
5627846 Drop-out location detection circuit
5627837 Apparatus and method for suppressing protection switching in a di...
5623599 Method and apparatus for processing a synchronizing marker for an...
5623497 Bit error rate measurement apparatus
5623498 User programmable test arrangement for a telecommunications netwo...
5621737 Communication system with link margin control and method
5621736 Formatting of a memory having defective cells
5619509 Apparatus and methods for testing transmission equipment and a se...
5617425 Disc array having array supporting controllers and interface
5615223 PPM decoder utilizing drop-out location information
5612961 Method and system for verification of the baud rate for an asynch...
5611045 Detecting the presence of a device on a computer system bus by me...
5610923 Method and device for finding spurious maintenance messages
5608741 Fast parity generator using complement pass-transistor logic
5606563 Programmable jump window for sonet compliant bit error monitoring
5604756 Testing device for concurrently testing a plurality of semiconduc...
5600785 Computer system with error handling before reset
5598424 Error detection structure and method for serial or parallel data ...
5592492 Convolutional interleaving/de-interleaving method and apparatus f...
5590135 Testing a sequential circuit
5590274 Multi-volume audit trails for fault tolerant computers
5586123 Interface and loopback circuit for character based computer perip...
5583874 10Base-T portable link tester
5581561 Random bit diagnostic for a high resolution measurement system
 
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