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Walt Disney was no Mickey Mouse inventor. He devised a serious animation camera which he patented. With the device, his company created "Snow White".
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| Number | Title | Issue Date |
| 6721817 | Original equipment manufacturer identification for configurable electronic hardware A configurable hardware for coupling to one of a plurality of hardware. Each of the plurality of hardware has a type. The configurable hardware includes a memory for storing an ID. The ID identifies the type of the hardware coupled to the configurable hardware. ... | 04/13/2004 |
| 6625679 | Apparatus and method for converting interrupt transactions to interrupt signals to distribute interrupts to IA-32 processors An apparatus and method for distributing interrupts to Intel.RTM. Architecture (IA)-32 processors includes a system bus having a number of nodes. Each node includes a bridge that couples the system bus to a processor bus. The processor bus may include mul... | 09/23/2003 |
| 6608464 | Integrated power source layered with thin film rechargeable batteries, charger, and charge-control A self-contained, small, lightweight, portable, renewable, modular integrated power source. The power source consists of a recharging means such as solar cells that are laminated onto a rechargeable energy source such as a solid state polymer battery whic... | 08/19/2003 |
| 6591320 | Method and system for selective disablement of expansion bus slots in a multibus data processing system A method and system for eliminating peripheral device conflicts in a multibus data-processing system which includes a Peripheral Component Interconnect (PCI) plus having multiple slots for interconnecting peripheral devices in an automatically derived con... | 07/08/2003 |
| 6583599 | Method and apparatus for controlling battery charging in a hybrid electric vehicle A starter/alternator system (24) for hybrid electric vehicle (10) having an internal combustion engine (12) and an energy storage device (34) has a controller (30) coupled to the starter/alternator (26). The controller (30) has a state of charge manager (... | 06/24/2003 |
| 6560665 | Embedding firmware for a microprocessor with configuration data for a field programmable gate array An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel p... | 05/06/2003 |
| 6557121 | Method and system for fault isolation for PCI bus errors Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input/output (I/O) subsystem formed by a plurality of I/O dev... | 04/29/2003 |
| 6557068 | High speed peripheral interconnect apparatus, method and system A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The ex... | 04/29/2003 |
| 6553490 | Computer system including local computer with capability to automatically update operating system or application program from network server A local computer stores a current program such as an operating system or an application. A network server stores a latest program which is a latest version of the current program, and an identifier program for generating an identification corresponding to... | 04/22/2003 |
| 6553492 | Client-server system, server access authentication method, memory medium stores server-access authentication programs, and issuance device which issues the memory medium contents It is necessary to authenticate each access by permitting or refusing it when a client makes an access to a server in a client-server system in which clients and servers are interconnected via a network. The client utilizes memory medium which stores both... | 04/22/2003 |
| 6553500 | Pulsed power supply unit for computer systems A power supply unit for a computer system is proposed which has at least one data memory unit, which provides data specific to the power supply unit, for system controllers in the computer system. This achieves the object of offering the capability of ens... | 04/22/2003 |
| 6546414 | Method, system and program products for copying coupling facility lock structures Lock structures of a shared storage processor of a computing environment are copied. A copy operation for a lock structure of the shared storage processor is initiated. Although the lock structure is owned by an exploiter of the lock structure, one or mor... | 04/08/2003 |
| 6539451 | Data storage system having master-slave arbiters A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface has a memory with a high address memory section and a low address memory section. A plurality of directors control data transfer be... | 03/25/2003 |
| 6539450 | Method and system for adjusting isochronous bandwidths on a bus A method and system for adjusting the bandwidth allocated for isochronous data traffic on an interconnected data bus is disclosed. The present system uses an isochronous resource manager (IRM) to sense a bandwidth change request from a talker. The IRM ins... | 03/25/2003 |
| 6535948 | Serial interface unit A serial interface unit having an input shift register adapted to receive a serial input data from a serial data stream, and a destination request module. The input shift register converting the serial input data into a parallel input data. The input shif... | 03/18/2003 |
| 6535976 | Initial program load in data processing network Methods of booting a client data processing system attached to a control data processing system in a data processing network. At power-on or re-boot of a client system, an initial program load request is issued from the client system onto the network and ... | 03/18/2003 |
| 6535944 | Hot plug control of MP based computer system A method of servicing a computer system without interrupting operation of the computer system, by connecting a computer component to a board of the computer system, detecting connection of the computer component to the system board using a control circuit... | 03/18/2003 |
| 6535941 | Method and apparatus for avoiding data bus grant starvation in a non-fair, prioritized arbiter for a split bus system with independent address and data bus grants A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, e... | 03/18/2003 |
| 6532506 | Communicating with devices over a bus and negotiating the transfer rate over the same A system having a first device and a second device coupled to a single wire bus is described. The second device is operable to receive power from the single wire bus that is due to the first device driving the bus. The second device also communicates with... | 03/11/2003 |
| 6529980 | Superposition of host bridge status onto an existing request/grant signaling protocol A protocol for superimposing status information onto an arbitration scheme between a first bus agent and a second bus agent. One embodiment of the arbitration scheme uses a grant signal and a request signal to arbitrate for use of a bus. The second bus ag... | 03/04/2003 |
| 6529979 | Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgement A method and apparatus for transferring data using an on-chip bus is presented. A data transaction consisting of an address and data packet is transmitted on an on-chip bus which is a two-wire serial bus consisting of an address line and a data line that ... | 03/04/2003 |
| 6529978 | Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings An apparatus, program product and method to dynamically control the bindings between Input/Output Adaptors (IOA's) and Input/Output Processors (IOP's) in a hierarchical I/O interface of a computer, such that an IOA can be dynamically reassigned from one I... | 03/04/2003 |
| 6529984 | Dual phase arbitration on a bus A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that ... | 03/04/2003 |
| 6529975 | Method and apparatus for addressing and controlling exspansion devices through an AC-link and a codec In one embodiment, a single designated register in a codec is utilized by a controller to address and control a large number of expansion registers belonging to various expansion devices. The controller can write to or read from the designated register th... | 03/04/2003 |
| 6529974 | Method for exchanging digital data between electronic cards and corresponding connection system The connection system between electronic cards comprises at least a base card (CB) comprising a printed circuit having a set of tracks for transferring electric signals, at least two base connectors (CO2-CO5) connected on said set of tracks and each capab... | 03/04/2003 |
| 6526513 | Architecture for dynamic permissions in java An architecture for extending the Java security model to allow a user or administrator to grant permissions dynamically. By itself, the Java 2 security model does not allow additions to the collections of policy permissions after they have been loaded fro... | 02/25/2003 |
| 6526516 | Power control system and method for distribution of power to peripheral devices In a system to which a plurality of devices are connected, each device has heretofore required a connector for an AC adapter and a connector for a signal line. Further, in order to arrange it so that the amount of power supplied to the overall system will... | 02/25/2003 |
| 6526464 | Mechanism to expand address space of a serial bus A computer system having a primary serial bus and one or more serial sub-busses separated from the primary serial bus by gating devices is described. By selectively enabling different gating devices (thereby coupling one serial sub-bus to the primary seri... | 02/25/2003 |
| 6523075 | Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource A system for preventing bus contention in a multifunction integrated circuit during testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The... | 02/18/2003 |
| 6523125 | System and method for providing a hibernation mode in an information handling system To provide an information handling system and a method of controlling the same which allows the state of the system to be saved without destructing other user data on an external storage device. When a predetermined event occurs, the system saves hibernat... | 02/18/2003 |
| 6523111 | Remote configuration/setup of computer systems operated as embedded controllers without keyboard or video display resources Method and program product operable on a computer for changing configuration/setup parameters in an embedded controller type X86 based computer system, the system characterized by the absence of any keyboard or video display, from a remote terminal. The p... | 02/18/2003 |
| 6523112 | Operating system software boot program execution method A data server having a plurality of hot replaceable processing unit modules. Each module includes a motherboard having plugged therein: a CPU; a main memory; an I/O adapter card, and an interconnect printed board, electrically connected to the motherboard... | 02/18/2003 |
| 6519668 | Additional extension device having universal applicability A device for extending functions of a computer connected thereto adds a new function to functions of an existing extension unit. The device includes a non-volatile memory and a new extension unit connected to the non-volatile memory and capable of being c... | 02/11/2003 |
| 6519671 | Method of network configuration, method and apparatus for information processing, and computer-readable media A bridge manager (bridge management equipment) is automatically determined. In a network, bridges 51 to 54 are configured by connecting portals 41 to 48 respectively connected to buses 11 to 15 and the different buses 11 to 15 are connected via the bridge... | 02/11/2003 |
| 6519665 | Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request A data processing system includes at least first and second nodes and a segmented interconnect having coupled first and second segments. The first node includes the first segment and first and second agents coupled to the first segment, and the second nod... | 02/11/2003 |
| 6516367 | Method and system for detecting bus device configuration changes A method, system and computer program product are provided for detecting the presence of devices, particularly hot plug devices, connected to a bus both during start-up of a computer system and while the system is running. At start-up, and periodically th... | 02/04/2003 |
| 6516418 | Portable computer having universal serial bus ports controlled power supply and a method of the same A portable computer system with universal serial bus (USB) port or ports and a method for controlling power of the universal serial bus (USB) port is described. When the main power of the portable computer system is supplied from a battery rather than an ... | 02/04/2003 |
| 6516377 | Self-configuring modular electronic system In an electronic system, an arithmetic device is provided between successive bus terminals or between successive modules, respectively, with an identification signal applied to a bus input that is routed from one bus terminal to the next bus terminal unti... | 02/04/2003 |
| 6513080 | High speed bus system and method for using voltage and timing oscillating references for signal detection A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit fo... | 01/28/2003 |
| 6513089 | Dual burst latency timers for overlapped read and write data transfers The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority level signals. The arbitration for use of the read and write b... | 01/28/2003 |
