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| Number | Title | Issue Date |
| 5585671 | Reliable low thermal resistance package for high power flip clip ICs A flip-chip IC package (10) provides a thermally-conductive lid (20) attached to a backside of the chip (12) by a die attach layer (18) of a predetermined thickness range. A rim (22), preferably KOVAR iron-nickel alloy, is formed on the lid (20) with a de... | 12/17/1996 |
| 5567987 | Semiconductor device having a multi-layer metallization structure The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is forme... | 10/22/1996 |
| 5543646 | Field effect transistor with a shaped gate electrode A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semic... | 08/06/1996 |
| 5510652 | Polishstop planarization structure The invention provides a method for producing a substantially planar surface overlying features of a semiconductor structure. The method comprises forming alternating layers of a hard polishing material and a soft polishing material over the features of t... | 04/23/1996 |
| 5502324 | Composite wiring layer An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite latera... | 03/26/1996 |
| 5491352 | Semiconductor device having peripheral metal wiring At a peripheral area of a semiconductor chip where active elements are not formed, a layer underlying a power supply wiring or ground wiring is provided with an uneven surface. The uneven or corrugated surface at the interface between the wiring and the u... | 02/13/1996 |
| 5479054 | Semiconductor device with improved planarization properties A polycrystalline silicon film is formed on the surface of a semiconductor substrate. An oxide film having a first impurity concentration is formed to cover the polycrystalline silicon film. A polycrystalline silicon film and a refractory metal silicide a... | 12/26/1995 |
| 5477082 | Bi-planar multi-chip module A bi-planar multi-chip package has die mounted on both sides of an insulating flexible carrier. The die are located in two parallel planes, with the flexible carrier located on a third plane between the two die planes. The die are mounted with the active ... | 12/19/1995 |
| 5477087 | Bump electrode for connecting electronic components The present invention relates to connecting electronic components using bump electrodes to connect electronic components such as semiconductors with the patterning electrodes of a circuit board. In order to prevent deterioration in connecting reliability ... | 12/19/1995 |
| 5475265 | Semiconductor device including gold interconnections where the gold grain size is a function of the width of the interconnections In a semiconductor device having gold interconnections for connecting elements formed on a substrate with each other, the improvement is that the average dimension of gold grains constituting the gold interconnections is determined to be 0.17 through 0.25... | 12/12/1995 |
| 5475240 | Contact structure of an interconnection layer for a semiconductor device and a multilayer interconnection SRAM A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the open... | 12/12/1995 |
| 5475236 | Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process A semiconductor chip for mounting on a package substrate by a flip-chip process includes a plurality of electrode pads of a first group provided on a major surface of the semiconductor chip for external electrical connection such that the electrode pads o... | 12/12/1995 |
| 5475260 | Electronic read-only module The electronic read-only memory has an inner and an outer casing. The inner casing is located on a secondary circuit board, from whose edge projecting laterally from the inner casing project contact elements for producing a plug contact with the contact c... | 12/12/1995 |
| 5475267 | Multilayer interconnection structure for a semiconductor device An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole... | 12/12/1995 |
| 5473188 | Semiconductor device of the LOC structure type having a flexible wiring pattern In a semiconductor device of the LOC (lead on chip) structure type according to the present invention, one ends of external connector leads are fixed to an insulating tape and the other ends thereof extend outside the insulating tape. Inner leads for inte... | 12/05/1995 |
| 5473193 | Package for parallel subelement semiconductor devices A package for semiconductor devices with plural subelements and method of packaging. Semiconductor power devices may include plural subelements to increase device manufacturing yield. Each subelement is separately contacted through the lid of the package ... | 12/05/1995 |
| 5471080 | Field effect transistor with a shaped gate electrode A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semic... | 11/28/1995 |
| 5471096 | Solder interconnection from a composition containing a mixture of dicyanates Compositions containing bisphenol M dicyanate, prepolymer thereof, or mixtures thereof, and 4,4'-ethylidene bisphenol dicyanate, prepolymer thereof or mixtures thereof; and filler having maximum particle size of 20 microns and being substantially free of ... | 11/28/1995 |
| 5471086 | Semiconductor device having piezo resistance Disclosed herein a semiconductor pressure sensor, which is capable of carrying out temperature compensation in high accuracy, having a piezo resistance layer consisting of a single crystal layer formed by lateral seeding. In this semiconductor pressure se... | 11/28/1995 |
| 5465007 | High frequency transistor with reduced parasitic inductance A semiconductor device includes a transistor mounted on the top surface of a substrate. A metal sheet is disposed on a metallized electrode on the substrate to which the emitter, for example, of the transistor is electrically connected. The emitter is ele... | 11/07/1995 |
| 5465005 | Polysilicon resistor structure including polysilicon contacts An integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating... | 11/07/1995 |
| 5463242 | Thin film circuits with high density connector A method of fabricating a high density thin film circuit includes the step of bonding a high density connector having a plurality of electrical connection lines with a wafer having a plurality of electrical contact pads arranged in a pattern with a pitch ... | 10/31/1995 |
| 5463233 | Micromachined thermal switch A monolithic micromachined temperature switch obviates the necessity of assembling discrete components and also allows the temperature switch to be disposed in a relatively small package. In one embodiment of the invention, the temperature switch includes... | 10/31/1995 |
| 5461394 | Dual band signal receiver A dual band signal receiver is provided with relatively coaxial antenna assemblies electromagnetically coupled to respective upper and lower band rectangular waveguides and ports through suitable polarization switching assemblies. The upper band rotatable... | 10/24/1995 |
| 5459353 | Semiconductor device including interlayer dielectric film layers and conductive film layers A first interlayer dielectric film layer is formed on a P-type semiconductor substrate. The first interlayer dielectric film is made of a BPSG film formed by the method of atmospheric pressure chemical vapor deposition. First connection holes are formed a... | 10/17/1995 |
| 5459335 | Semiconductor substrate having a thin film semiconductor layer bonded on a support substrate through an adhesive layer A thin film semiconductor substrate for a display device includes a thin film semiconductor circuit layer formed on a single crystal semiconductor substrate and a support substrate formed over the thin film semiconductor circuit layer. An adhesive layer m... | 10/17/1995 |
| 5459346 | Semiconductor substrate with electrical contact in groove A semiconductor substrate comprises a foundation, a semiconductor monocrystalline film formed on the foundation, and a high-melting-point metal film or a high-melting-point metal alloy film disposed in at least part of a region between the semiconductor m... | 10/17/1995 |
| 5457343 | Carbon nanotubule enclosing a foreign material The invention provides a nanometer sized carbon tubule enclosing a foreign material except for carbon. The carbon tubule comprises a plurality of tubular graphite monoatomic sheets coaxially arranged. The foreign material is introduced through a top porti... | 10/10/1995 |
| 5455438 | Semiconductor integrated circuit device in which kink current disturbances of MOS transistors are suppressed Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transisto... | 10/03/1995 |
| 5455455 | Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby A method for producing integrated circuit devices including the steps of producing a plurality of integrated circuits on a wafer, each of the integrated circuits including a multiplicity of pads and thereafter slicing the wafer, thereby to define a plural... | 10/03/1995 |
| 5455452 | Semiconductor package having an LOC structure A semiconductor integrated circuit device and method of making same wherein recessed bus bar regions are provided in an elongated bus bar to accommodate bonding wires which couple the device's chip pads and associated inner leads. Fillets are formed of in... | 10/03/1995 |
| 5455446 | Leaded semiconductor package having temperature controlled lead length A plastic leaded semiconductor package (20) has a semiconductor device (614) encapsulated in the package and mounted to a lead frame (612). The lead frame has a plurality of leads (622) that extend beyond the body (610) of the encapsulated package. Each o... | 10/03/1995 |
| 5455439 | Semiconductor device which moderates electric field concentration caused by a conductive film formed on a surface thereof The present invention relates to a semiconductor device which is fabricated in simple process steps and which prevents deterioration in a breakdown voltage. Two diffusion regions are formed in space in a surface of an n- type layer. The diffus... | 10/03/1995 |
| 5455445 | Multi-level semiconductor structures having environmentally isolated elements A plurality of individual device layers having conductive regions extending therethrough are bonded together before or after one or more circuit elements have been fabricated on each one. Groups of device layers are formed by electrochemically anodizing a... | 10/03/1995 |
| 5453639 | Planarized semiconductor structure using subminimum features Improved, planarized semiconductor structures are described. They are prepared by a method which involves the creation of a series of subminimum (i.e., 50 to 500 Angstroms thick) silicon pillars extending vertically upward from the base of a wide trench, ... | 09/26/1995 |
| 5453752 | Compact broadband microstrip antenna A compact broadband microstrip antenna for mounting to one side of a ground plane comprises a closed (usually circular) array of antenna elements positioned to one side of a substrate for spacing the antenna elements a selected distance above the ground p... | 09/26/1995 |
| 5451804 | VLSI device with global planarization A new method of fabricating an integrated circuit which maintains global planarization throughout the process flow is achieved. Trenched isolation regions are formed within a silicon substrate. Trenched polysilicon gate electrodes are formed within the si... | 09/19/1995 |
| 5448102 | Trench isolation stress relief In a microelectronic device formed on a substrate 12, a pair of trenches 30, 36 branch at their intersection to provide branches 31-34 surrounding a sacrificial island 42. Sacrificial island 42 may comprise substrate material or other material or a void f... | 09/05/1995 |
| 5448106 | Thin semiconductor integrated circuit device assembly A plurality of electrodes are formed on one surface of a semiconductor integrated circuit chip. A plurality of leads are arranged around the chip. Each of the electrodes and one end of each of the leads are connected. The electrodes and the chip are sandw... | 09/05/1995 |
| 5448255 | Dual band down converter for MMDS/MDS antenna A dual band MDS/MMDS down converter receiving system wherein the support boom of a semi-parabolic antenna contains the down converter electronics. Located at the focal area of the semi-parabolic antenna are a pair of driven feed elements which are connect... | 09/05/1995 |
