| Patent No. | Patent Title: |
| 8191035 | Tool with graphical interconnect matrix |
| 8191020 | Graphical user aid for technology migration and associated method... |
| 8185855 | Capacitor-cell, integrated circuit, and designing and manufacturi... |
| 8181148 | Method for identifying and implementing flexible logic block logi... |
| 8181132 | Validating one or more circuits using one or more grids |
| RE43393 | Method and system for creating and programming an adaptive comput... |
| 8181125 | System and method for providing compliant mapping between chip bo... |
| 8176443 | Layout of printable assist features to aid transistor control |
| 8176462 | Method and apparatus for generating test patterns for use in at-s... |
| 8171437 | Automated convergence of ternary simulation by saturation of deep... |
| 8166429 | Multi-layer distributed network |
| 8161428 | Method of predicting reliability of semiconductor device, reliabi... |
| 8161422 | Fast and accurate method to simulate intermediate range flare eff... |
| 8146039 | Optimal distance based buffer tree for data path and clock |
| 8146031 | Method for generating and evaluating a table model for circuit si... |
| 8141028 | Structure for identifying and implementing flexible logic block l... |
| 8141022 | Method and apparatus for hierarchical design of semiconductor int... |
| 8136060 | Method and mechanism for identifying and tracking shape connectiv... |
| 8136058 | Method and system for representing geometrical layout design data... |
| 8132129 | Method for computing the sensitivity of a VLSI design to both ran... |
| 8132139 | Method of designing semiconductor device and design program |
| 8132133 | Automated isolation of logic and macro blocks in chip design test... |
| 8127258 | Data processing device design tool and methods |
| 8122390 | Charged particle beam writing apparatus, and apparatus and method... |
| 8122386 | Dummy pattern placement apparatus, method and program and semicon... |
| 8122397 | Method and system for mapping source elements to destination elem... |
| 8122396 | Local searching techniques for technology mapping |
| 8117569 | Method and mechanism for implementing a minimum spanning tree |
| 8117586 | Printed circuit board layout system and method thereof |
| 8117573 | Verification-scenario generating apparatus, verification-scenario... |
| 8117566 | Method and system for representing manufacturing and lithography ... |
| 8112727 | Method and system product for implementing uncertainty in integra... |
| 8108807 | Delay time adjusting method of semiconductor integrated circuit |
| 8108812 | Register retiming technique |
| 8108813 | Structure for a circuit obtaining desired phase locked loop duty ... |
| 8108809 | Routing analysis method, logic synthesis method and circuit parti... |
| 8108802 | Method for forming arbitrary lithographic wavefronts using standa... |
| 8108821 | Reduction of logic and delay through latch polarity inversion |
| 8108811 | Validation of electrical performance of an electronic package pri... |
| 8103982 | System and method for statistical design rule checking |
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