Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 6170997 | Method for executing instructions that operate on different data types stored in the same single logical register file A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to... | 01/09/2001 |
| 6118936 | Signaling network management system for converting network events into standard form and then correlating the standard form events with topology and maintenance information A signaling network management system (SNMS) collects network topology, traffic, performance and fault information, correlates that information and displays the information to system operators. It includes a distributed client/server platform that receive... | 09/12/2000 |
| 6115545 | Automatic internet protocol (IP) address allocation and assignment A network device connected to a local network is configured using a module operating within a console connected to the local network. Once activated, the module obtains an unused network address. After obtaining the unused network address, the console wai... | 09/05/2000 |
| 6085261 | Method and apparatus for burst protocol in a data processing system A data processing system (10) capable of burst transfers having an external bus interface (30) which allows termination of a burst transfer prior to completion of the burst transaction. The present invention offers a method of terminating a burst transact... | 07/04/2000 |
| 6072942 | System and method of electronic mail filtering using interconnected nodes A system and method for filtering electronic mail messages is described. A message is received an processed through a one or more filter flows. Each filter flow is comprised of one or more self-contained nodes which can be combined in whatever order is re... | 06/06/2000 |
| 6073230 | Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in a first clock cycle. The first index and first way select a... | 06/06/2000 |
| 6064805 | Method, system, and computer program product for intraconnect data communication using buffer pools and buffer pool management A method, system, and computer program product specifies a communication intraconnect architecture that supports a pull model based data communication where data is sent to a receiver along with a memory address (a receiver buffer address or a reference t... | 05/16/2000 |
| 6049866 | Method and system for an efficient user mode cache manipulation using a simulated instruction A method and a system for fast user mode cache synchronization. The present invention is implemented on a computer system having a instruction cache. The system of the present invention detects a simulated instruction from a process running on the compute... | 04/11/2000 |
| 6044205 | Communications system for transferring information between memories according to processes transferred with the information An automated communications system operates to transfer data, metadata and methods from a provider computer to a consumer computer through a communications network. The transferred information controls the communications relationship, including responses ... | 03/28/2000 |
| 6035118 | Mechanism to eliminate the performance penalty of computed jump targets in a pipelined processor A technique for eliminating the performance penalty of implementing jump instructions in a deeply pipelined processor includes a pipeline having a signal for indicating that the top of the address return stack has been updated by an address moved to the r... | 03/07/2000 |
| 6006030 | Microprocessor with programmable instruction trap for deimplementing instructions A microprocessor includes a programmable instruction trap that can be used to deimplement instructions that lead to erroneous results. Upon discovery of a logic design defect, a microprocessor manufacturer can distribute an updated exception handler and a... | 12/21/1999 |
| 6003122 | Direct memory access controller An alignment logic circuit transferring segments of data from a first storage device to a second storage device is provided. The alignment logic circuit includes a first and second alignment stages, and an alignment control logic that controls the first a... | 12/14/1999 |
| 6000028 | Means and apparatus for maintaining condition codes in an unevaluated state A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a n... | 12/07/1999 |
| 5974518 | Smart buffer size adaptation apparatus and method Disclosed is a network device having a shared memory, a controller for storing Ethernet frames in frame buffers using data chaining to divide up at least the larger frames over a plurality of same sized buffers in the shared memory, wherein there is a tra... | 10/26/1999 |
| 5974240 | Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution In response to dispatching a condition register modifying instruction to an execution unit, a condition register rename buffer is associated with such a condition register modifying instruction. The instruction is then executed in the execution unit. Foll... | 10/26/1999 |
| 5974539 | Three input arithmetic logic unit with shifter and mask generator A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special da... | 10/26/1999 |
| 5966509 | Network management device A network management device for managing a plurality of network elements has a network element management data acquisition unit for acquiring, in stages, various management data possessed by the network elements when a session with a network element is re... | 10/12/1999 |
| 5961635 | Three input arithmetic logic unit with barrel rotator and mask generator A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored i... | 10/05/1999 |
| 5963720 | Method and system for expediting transfer of data over a network using an additional field A system and method for expediting data processing in a computer system including a network controller and a driver is disclosed. The method and system first provide a hardware structure. The hardware structure has a first plurality of fields and correspo... | 10/05/1999 |
| 5960174 | Arbitration method for a communication network A communications network is used to couple weld controllers and different operator interface units together, regardless of their data structures. An arbitration system provides a means for one operator interface unit to communicate to a selected weld cont... | 09/28/1999 |
| 5953513 | Recording and reproducing device for recording and reproducing information from different kinds of storage media having different sector formats The recording and reproducing apparatus comprises an Small Computer System Interface (SCSI) controller, an optical disc device, a magnetic disc device, a disc controller which controls the optical disc device and the magnetic disc device, connectors which... | 09/14/1999 |
| 5946468 | Reorder buffer having an improved future file for storing speculative instruction execution results A reorder buffer for a microprocessor comprising a control unit, an instruction storage, and future file. The future file has storage locations associated with each register implemented in the microprocessor. The future file is configured to store a reord... | 08/31/1999 |
| 5944798 | System and method for arbitrated loop recovery A computer system with a plurality of devices compatible with the Fibre Channel Protocol. The computer system is provided with the capability to recover from a loop hang condition resulting from an unresponsive communication link in an Arbitrated Loop. Th... | 08/31/1999 |
| 5943494 | Method and system for processing multiple branch instructions that write to count and link registers A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers allocated to the count and link registers. The method and system... | 08/24/1999 |
| 5943500 | Long latency interrupt handling and input/output write posting An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other int... | 08/24/1999 |
| 5937164 | Method and apparatus of secure server control of local media via a trigger through a network for instant local access of encrypted data on local media within a platform independent networking system A method of triggering video imaging and/or audio data on a "HyperCD" (CD-ROM) via a trigger through a network for instant local access of encrypted data on local media. The CD-ROM contains video/audio files that have been crippled by removing the critica... | 08/10/1999 |
| 5937177 | Control structure for a high-speed asynchronous pipeline Apparatus is disclosed for asynchronously controlling a pipeline. The control circuitry includes an alternating chain of control circuits and detection circuits. When a full control circuit precedes an empty control circuit in the chain, indicating that t... | 08/10/1999 |
| 5937163 | Method and system at a host node for hierarchically organizing the links visited by a world wide web browser executing at the host node A host node is provided with an I/O port and a display monitor. The I/O port transmits packets to a specific one of the remotely accessible server nodes containing a request for information. In response, the I/O port receives packets containing requested ... | 08/10/1999 |
| 5930508 | Method for storing and decoding instructions for a microprocessor having a plurality of function units A method and apparatus for compacting VLIW instructions in a processor having multiple functional units and including a buffer for storing compacted instructions, wherein NOP codes are eliminated from the compacted instruction and each compacted instructi... | 07/27/1999 |
| 5930489 | Microprocessor configured to detect memory operations having data addresses indicative of a boundary between instructions sets A microprocessor configured to detect a memory operation having a predefined data address is provided. The predefined data address indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, a second memory operation ... | 07/27/1999 |
| 5930514 | Self-deletion facility for application programs A facility for permitting self-deletion of application programs from a computer's mass-storage device is disclosed. The facility includes a component that tracks new files added in the course of program installation, as well as any modifications to perman... | 07/27/1999 |
| 5930492 | Rapid pipeline control using a control word and a steering word A pipeline conveys a control word and a steering word with each instruction. The control word specifies the control signals for the instruction at each pipeline stage. The steering word specifies the routing of the instruction through the pipeline stages.... | 07/27/1999 |
| 5930471 | Communications system and method of operation for electronic messaging using structured response objects and virtual mailboxes A communications system facilitates transactions between a sender and a plurality of recipients as part of an electronic messaging system. Messaging means enable a sender to form an electronic template containing a message in the form of a structured resp... | 07/27/1999 |
| 5930522 | Invocation architecture for generally concurrent process resolution An invocation architecture for generally concurrent process resolution comprises a plurality of interconnected processors, some of the processors being homogeneous processors and others of the processors being special purpose processors. Each homogeneous ... | 07/27/1999 |
| 5926652 | Matching of wild card patterns to wild card strings associated with named computer objects method of matching computer wild card patterns involves comparing first and second character strings associated with named objects residing on a computer system to determine whether the first character string defines a first group of computer objects whic... | 07/20/1999 |
| 5920714 | System and method for distributed multiprocessor communications In a tightly coupled communication scheme based on a common shared resource circuit having a plurality of shared information registers and adapted particularly to a multiprocessing system having 2N CPUs, a method of performing a read-and-modify... | 07/06/1999 |
| 5918034 | Method for decoupling pipeline stages The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued f... | 06/29/1999 |
| 5918013 | Method of transcoding documents in a network environment using a proxy server A method of providing a document to a client coupled to a server is provided. The server provides a number of Internet services to the client, including functioning as a caching proxy on behalf of the client for purposes of accessing the World Wide Web. T... | 06/29/1999 |
| 5915109 | Microprocessor for processing a saturation instruction of an optional-bit length value A microprocessor having a saturation operation unit comprising a decoder 220 for decoding a 4-bit saturation operation bit length data item into a 16-bit value, a decoder 221 for decoding a 5-bit saturation operation bit length data item into 1 to a 32-bi... | 06/22/1999 |
| 5915110 | Branch misprediction recovery in a reorder buffer having a future file A reorder buffer for a microprocessor comprising a control unit, an instruction storage, and future file. The future file has storage locations associated with each register implemented in the microprocessor. The future file is configured to store a reord... | 06/22/1999 |
