Quotables
"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 8189416 | Semiconductor memory device The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the me... | 05/29/2012 |
| 8189410 | Memory device and method thereof A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of ... | 05/29/2012 |
| 8189425 | Semiconductor memory device A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control si... | 05/29/2012 |
| 8174922 | Anti-fuse memory cell and semiconductor memory device An anti-fuse memory cell includes: a first transistor connected with a word line and configured to output a second voltage based on a first voltage supplied to the word line in a write mode; a second transistor connected with a bit line, and configured to output a t... | 05/08/2012 |
| 8174915 | Semiconductor memory device and method of testing the same A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is ... | 05/08/2012 |
| 8174865 | Memory devices and wireless devices including the same A memory device includes a plurality of memory bit lines connected to a plurality of memory cells, a plurality of reference bit lines connected to a plurality of reference cells and a reference bit line selection circuit. The memory bit lines has a first pattern and... | 05/08/2012 |
| 8174907 | Semiconductor device having data input/output unit connected to bus line To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fo... | 05/08/2012 |
| 8174905 | Programming orders for reducing distortion in arrays of multi-level analog memory cells A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are pro... | 05/08/2012 |
| 8171242 | Systems and methods for scheduling a memory command for execution based on a history of previously executed memory commands A memory system is operated by maintaining a queue of memory commands to be executed, maintaining a list of previously executed memory commands, comparing local information associated with the commands to be executed with local information associated with the list o... | 05/01/2012 |
| 8169849 | Memory system and method with serial and parallel modes Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links o... | 05/01/2012 |
| 8169820 | Use of symmetric resistive memory material as a diode to drive symmetric or asymmetric resistive memory A crosspoint array is made up of a plurality of bitlines and wordlines and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline, and each crossbar element comprising at least a phase change material used as a r... | 05/01/2012 |
| 8164967 | Systems and methods for refreshing non-volatile memory Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern... | 04/24/2012 |
| 8149640 | Differential sense amplifier The differential sense amplifier according to one aspect of the present invention includes a first differential amplification unit that detects a difference between the pair of complementary signals inputted from a first bit line and a second bit line, a second diff... | 04/03/2012 |
| 8144541 | Method and apparatus for adjusting and obtaining a reference voltage A method for adjusting a reference voltage is provided, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the actual reference voltage with a benchmark value to obtain a deviation... | 03/27/2012 |
| 8144533 | Compensatory memory system A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance. ... | 03/27/2012 |
| 8144523 | Semiconductor storage device A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a plurality of memory cells arranged in a matrix pattern, a plurality of word lines each provided so as to correspond to each line of the memory cells, a pluralit... | 03/27/2012 |
| 8144520 | Non-volatile memory device and method of reading data in a non-volatile memory device A non-volatile memory device includes a row decoder and a memory cell array. The row decoder generates a read voltage, and first, second and third drive voltages. The memory cell array includes a selected word line receiving the read voltage, a first neighboring wor... | 03/27/2012 |
| 8134870 | High-density non-volatile read-only memory arrays and related methods In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a cont... | 03/13/2012 |
| 8131970 | Compiler based cache allocation Techniques a generally described for creating a compiler determined map for the allocation of memory space within a cache. An example computing system is disclosed having a multicore processor with a plurality of processor cores. At least one cache may be accessible... | 03/06/2012 |
| 8130579 | Memory device and method of operation thereof Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a... | 03/06/2012 |
| 8125843 | Semiconductor memory device and method for testing the same A semiconductor memory device includes a memory cell array, a data input/output terminal, a data input/output circuit, and a test circuit. The data input/output circuit is provided between the memory cell array and the data input/output terminal. The data input/outp... | 02/28/2012 |
| 8120942 | Semiconductor memory device A memory array includes a memory cell, the memory cell being disposed between a first line and a second line and being configured by a variable resistor and a rectifier connected in series. The variable resistor is a mixture of silicon oxide (SiO2) and a transition ... | 02/21/2012 |
| 8120987 | Structure and method for decoding read data-bus with column-steering redundancy A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redun... | 02/21/2012 |
| 8117373 | VM host responding to initiation of a page swap by transferring pages from host-but-non-guest-addressable RAM to host-and-guest-addressable RAM A virtual-machine host responds to a guest operating system's initiation of a page swap by transferring a page from host-but-non-guest-addressable RAM to host-and-guest addressable RAM. ... | 02/14/2012 |
| 8111565 | Memory interface and operation method of it A memory interface includes a first delaying circuit configured to delay write data to be supplied to an input buffer; a second delaying circuit configured to delay read data read out from an output buffer; a data write circuit configured to supply said write data t... | 02/07/2012 |
| 8111573 | Nonvolatile semiconductor memory device and method of controlling the same Provided is a nonvolatile semiconductor memory device capable of performing a writing action for a memory cell at high speed. The device includes a memory cell array having a first sub-bank and a second sub-bank each having a plurality of nonvolatile memory cells ar... | 02/07/2012 |
| 8107307 | Memory device with data paths for outputting compressed data A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression modu... | 01/31/2012 |
| 8107315 | Double data rate memory device having data selection circuit and data paths A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amp... | 01/31/2012 |
| 8102722 | Data output device for semiconductor memory apparatus A data output device of a semiconductor memory apparatus includes detection means configured to detect a specified operation frequency range; pre-driving means configured to be inputted with signals; driving means configured to receive outputs of the pre-driving mea... | 01/24/2012 |
| 8102716 | Nonvolatile semiconductor memory device and method for performing verify write operation on the same Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined num... | 01/24/2012 |
| 8098511 | Reverse set with current limit for non-volatile storage A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resi... | 01/17/2012 |
| 8098522 | Non-volatile memory and operation method thereof An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage di... | 01/17/2012 |
| 8094494 | Memory and operation method therefor In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second readin... | 01/10/2012 |
| 8089794 | Precharge circuits and methods for content addressable memory (CAM) and related devices A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the... | 01/03/2012 |
| 8089818 | Nonvolatile semiconductor memory device A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connect... | 01/03/2012 |
| 8090911 | Selecting a target number of pages for allocation to a partition In an embodiment, a target number of discretionary pages for a first partition is calculated as a function of a number of physical page table faults, a number of sampled page faults, a number of shared physical page pool faults, a number of re-page-ins, and a ratio ... | 01/03/2012 |
| 8085613 | Power detecting circuit, portable device and method for preventing data loss In step S508, it is determined whether or not a power low signal SRC_LOSS outputted from the data latch is change. Generally Speaking, the power low signal SRC_LOSS outputted from the data latch would be changed according to the state of the power voltage of ... | 12/27/2011 |
| 8085601 | Programming method and initial charging method of nonvolatile memory device A programming method of a nonvolatile memory device includes precharging bit lines of the nonvolatile memory device based on loaded data, boosting channels corresponding to the respective precharged bit lines, after supplying word lines adjacent to a selected word l... | 12/27/2011 |
| 8081522 | Page buffer circuit for electrically rewritable non-volatile semiconductor memory device and control method Within a page buffer 14 which is coupled to a non-volatile memory cell array 10 and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array 10, at least one latch circuit 14 | 12/20/2011 |
| 8078796 | Method for writing to and erasing a non-volatile memory A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period. A long latency erase com... | 12/13/2011 |
