Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
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| Number | Title | Issue Date |
| 6178520 | Software recognition of drive removal or insertion in a storage system A method for detection of hot-swap of disk drives in a storage subsystem devoid of special circuits for such detection and for buffering of bus signals. Typical prior designs utilize special circuits such as disk drive canisters for physically and electro... | 01/23/2001 |
| 6163856 | Method and apparatus for file system disaster recovery A file disaster recovery system that employs geographical replication of data from a local site to remote site in a such a manner that file requests from clients of the local site can be handled by a file server on the remote site following a failover fro... | 12/19/2000 |
| 6154852 | Method and apparatus for data backup and recovery A method, computer program product and apparatus are provided for data backup and recovery in a computer system. The data backup and recovery method uses a plurality of tape drives in parallel. A unique token is associated with each data object being save... | 11/28/2000 |
| 6154849 | Method and apparatus for resource dependency relaxation A method and apparatus that allows flexibility in failure diagnosis, so that a single failure event received by a failure analysis system can affect the availability of different resources in different ways. The described embodiment also allows the depend... | 11/28/2000 |
| 6141755 | Firewall security apparatus for high-speed circuit switched networks A network firewall security apparatus that enables a very high degree of traffic selectability yet avoids the usual performance penalty associated with firewalls. This approach is specific to high-speed circuit switched networks, Asynchronous Transfer Mod... | 10/31/2000 |
| 6101621 | Logic circuit and method for designing the same A logic circuit with a pipelined structure has a plurality stage of combinational circuits and memory circuits such as flip-flops connected among the pipeline combinational circuits. The pipeline combinational circuits constituting a logic circuit is oper... | 08/08/2000 |
| 6101608 | Method and apparatus for secure remote wake-up of a computer over a network A method and related apparatus enables one station on a local area network (LAN) 24 to securely wake up another station on the LAN 24 although the stations may be physically remote from each other. A workstation 12, acting as a remote management console, ... | 08/08/2000 |
| 6073249 | Information processing system A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master pro... | 06/06/2000 |
| 6070240 | Computer access control A method of controlling a computer (12) system (10) comprising the steps of: disposing a computer (12) in an operating space and placing the computer (12) in a lockout mode to prevent operation of the computer (12) software by a user. A database (26) of a... | 05/30/2000 |
| 6070243 | Deterministic user authentication service for communication network A user authentication service for a communication network authenticates local users before granting them access to personalized sets of network resources. Authentication agents on intelligent edge devices present users of associated end systems with log-i... | 05/30/2000 |
| 6059450 | Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least t... | 05/09/2000 |
| 6061811 | Circuits, systems, and methods for external evaluation of microprocessor built-in self-test A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The dia... | 05/09/2000 |
| 6061805 | Method for executing an error recovery procedure An error recovery procedure (ERP) in a storage device such as a rotating magnetic hard disk drive is executed to the last step regardless of the established time-out period for an instruction, thereby more reliably recovering from errors. In accordance wi... | 05/09/2000 |
| 6061806 | Method and apparatus for maintaining automatic termination of a bus in the event of a host failure A method and apparatus for maintaining automatic termination of a bus in the event of failure of a host computer are disclosed. The method includes the steps of (a) powering a first termination control circuit and a first terminating circuit of the first ... | 05/09/2000 |
| 6061808 | Semiconductor memory device having a multibit test mode In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select ... | 05/09/2000 |
| 6055647 | Method and apparatus for determining computer system power supply redundancy level Apparatus, and an associated method, for determining the level of power supply redundancy in a modular computer system. Determination of the level of power supply redundancy is made dynamically, during on-line operation of the computer system. Reconfigura... | 04/25/2000 |
| 6055658 | Apparatus and method for testing high speed components using low speed test apparatus A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier ci... | 04/25/2000 |
| 6052807 | Multiple probe test equipment with channel identification Multi-channel measurement equipment identifies probe-to-channel correspondence by providing an identification (ID) terminal that can be touched by a probe whose channel correspondence is sought. A ID signal identifiable by its uncommon properties is prese... | 04/18/2000 |
| 6052806 | Method and apparatus for testing an integrated circuit device An integrated circuit device includes operational circuitry, for example, in the form of a memory for carrying out operations of the integrated circuit device. Additionally, at least one peripheral circuit is connected to the operational circuitry for car... | 04/18/2000 |
| 6052784 | Network discovery system and method A system and method for the discovery of information from a second resource by a first resource through a network using authentication. A discovery request message is received at the second resource. The discovery request message includes discovery reques... | 04/18/2000 |
| 6047390 | Multiple context software analysis A method for multiple context analysis of software applications in a multiprocessing (22, 23), multithreaded computer environment utilizes instrumentation code inserted (54, 55) into the applications. For each execution (67) of the application (60), a con... | 04/04/2000 |
| 6041423 | Method and apparatus for using undo/redo logging to perform asynchronous updates of parity and data pages in a redundant array data storage environment A method and apparatus for using undo/redo logging to perform asynchronous updates of parity and data pages in a redundant array data storage system is disclosed. The computer-implemented apparatus includes, 1) a redundant array data storage system having... | 03/21/2000 |
| 6038683 | Replicated controller and fault recovery method thereof A replicated controller and a fault recovery method therefor which can restore a faulty system to a normal state without interrupting operation of an equipment, even in an equipment controller performing processing with short operating periods. In a fault... | 03/14/2000 |
| 6035429 | Electronic circuit implementing component level disk drive An electronic circuit apparatus is provided comprising a component disk drive, and an electronic circuit implementing the component drive for local storage as an alternative to costlier solid state memory, wherein the electronic circuit has at least one f... | 03/07/2000 |
| 6035419 | Logical execution sequence error recovery method and system A recovery mechanism enabling recovery to be performed along logical execution paths of tasks processing within a computer system. Tasks executing within the computer system invoke one another in a logical invocation sequence. The recovery mechanism allow... | 03/07/2000 |
| 6032278 | Method and apparatus for performing scan testing A method and apparatus for providing a scan cell having a first input coupled to receive a data, a data output and a scan output. The scan cell being capable of transferring data to said scan output in response to a first scan clock and a second scan cloc... | 02/29/2000 |
| 6032270 | Data processor testing apparatus and a data processor testing method A data processor testing apparatus, in which, in an access instruction executing section, an instruction string to be tested for access to cache memories as an object for execution is previously prepared, access data on a memory is set in an instruction c... | 02/29/2000 |
| 6032257 | Hardware theft-protection architecture A method of theft protection for computers and computer related hardware. Warranty fraud, theft of proprietary technology, and hardware theft are minimized by encoding the hardware components such that a digitally authenticated handshake must be performed... | 02/29/2000 |
| 6032256 | Power controlled computer security system and method An I/O port locking computer security system is implemented in the power management module of the hardware-software interface program (BIOS). A hotkey sequence of keystrokes activates the portlock feature and a system management interrupt signal (SMI) is ... | 02/29/2000 |
| 6029263 | Interconnect testing using non-compatible scan architectures A method is provided that provides a test of an interconnect that communicates information between two digital circuits. One of the digital circuits is constructed to be "scannable" so that it at least includes scannable registers capable of applying sign... | 02/22/2000 |
| 6026506 | Concealing errors in transport stream data Method and apparatus for processing a data stream. Errors are concealed in the data stream by detecting loss or interruption of data delivery and signalling decoders to invoke error concealment.... | 02/15/2000 |
| 6023777 | Testing method for devices with status flags The present invention provides a design method and apparatus for improving the testing of devices having status flags that indicate when particular boundary conditions are met. The present invention enables a subset of the overall device architecture that... | 02/08/2000 |
| 6023773 | Multi-client test harness A multi-client test harness for testing first and second computer systems by executing a first test case on the first and second computer systems. The multi-client test harness includes a scheduler module. The scheduler module initiates execution of the f... | 02/08/2000 |
| 6023765 | Implementation of role-based access control in multi-level secure systems Role-based access control (RBAC) is implemented on an multi-level secure (MLS) system by establishing a relationship between privileges within the RBAC system and pairs of levels and compartments within the MLS system. The advantages provided by RBAC, tha... | 02/08/2000 |
| 6021512 | Data processing system having memory sub-array redundancy and method therefor One or more redundant sub-arrays (324) are added to a memory (316-322) of a data processing system (300) to allow a manufacturer to compensate for defects introduced during the fabrication phase of a semiconductor device upon which it is implemented. Each... | 02/01/2000 |
| 6021497 | Secured network system A secured network system which will allow only authorized users of the seed network system to access classified data provided by a secured network server. The secured network system includes a readykey controller which has connected thereto a plurality o... | 02/01/2000 |
| 6021513 | Testable programmable gate array and associated LSSD/deterministic test methodology A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into acco... | 02/01/2000 |
| 6018815 | Adaptable scan chains for debugging and manufacturing test purposes Scan chains to support debugging and manufacturing test modes for integrated circuit chips are made adaptable. Scan chains may be configured either in a multiple scan chain JTAG mode or in a multiple independent and parallel scan chain mode. The configura... | 01/25/2000 |
| 6016565 | Semiconductor device testing apparatus A strobe generator includes four strobe pulse generators generating original strobe pulses having the same frequency, respectively, and correspondingly, four logical comparator circuits, the number of which is identical to that of the strobe pulse generat... | 01/18/2000 |
| 6016559 | Multifunctional intergrated electronic product and method for preventing operation failure of the same A multifunctional integrated electronic product including a main microcomputer and a sub microcomputer configured as master and slave, respectively, is capable of preventing a malfunction caused by an error of data transmission between the microcomputers,... | 01/18/2000 |
