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| Number | Title | Issue Date |
| 5490260 | Solid-state RAM data storage for virtual memory computer using fixed-sized swap pages with selective compressed/uncompressed data store according to each data size A computer using virtual memory management employs a random-access type storage device such as a semiconductor memory for page swapping. The semiconductor memory is formatted to provide multiple partitions of varying block size, e.g., two block sizes, for... | 02/06/1996 |
| 5481691 | Cache page replacement using sequential LIFO and non-sequential LRU cast out A computer system includes a cache and a data storing system. The data storing system uses a write-once read-many (WORM) disk for storing computer data. The disk stores data in addressable so-called continuation chains. The cache stores pages of data in s... | 01/02/1996 |
| 5465342 | Dynamically adaptive set associativity for cache memories A memory cache system for high speed computers provides adaptive set associativity by means of which the degree of associativity of the cache is temporarily and dynamically increased in response to the behavior of the system. More particularly, one or mor... | 11/07/1995 |
| 5454099 | CPU implemented method for backing up modified data sets in non-volatile store for recovery in the event of CPU failure A CPU implemented method for managing the backup copying of data sets residing in non-volatile storage and for the recovery thereof in the event of CPU failure. The first step is to invoke a modified incremental backup copy policy using a small backup win... | 09/26/1995 |
| 5454091 | Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to regist... | 09/26/1995 |
| 5452420 | Intelligent network interface circuit for establishing communication link between protocol machine and host processor employing counter proposal set parameter negotiation scheme A communications interface circuit couples a host processor to a pair of serial communications links, During power-up the interface circuit negotiates a set of operating parameters with the host processor through a shared memory to establish the optimal c... | 09/19/1995 |
| 5452423 | Two-ROM multibyte microcode address selection method and apparatus An efficient organization for microcoded instruction sets which have processor operations in which not all the bits of an instruction word are required. The organization has two registers for receiving and holding the first and second byte of instructions... | 09/19/1995 |
| 5446856 | Circuitry and method for addressing global array elements in a distributed memory, multiple processor computer A method of addressing an arbitrary global element stored within a first local memory associated with a first processing device is described for a distributed memory computers which includes a multiplicity of processing devices each having an associated b... | 08/29/1995 |
| 5446854 | Virtual memory computer apparatus and address translation mechanism employing hashing scheme and page frame descriptor that support multiple page sizes A method and apparatus for providing address translations for a computer system having a virtual memory that is mapped onto physical memory. The apparatus has at least one page frame descriptor (PFD) for describing a contiguous portion of physical memory,... | 08/29/1995 |
| 5442758 | Apparatus and method for achieving reduced overhead mutual exclusion and maintaining coherency in a multiprocessor system utilizing execution history and thread monitoring A substantially zero overhead mutual-exclusion apparatus and method (90, 120) is provided that allows concurrent reading and updating data while maintaining data coherency. That is, a data reading process executes the same sequence of instructions that wo... | 08/15/1995 |
| 5440718 | Single semiconductor substrate RAM device utilizing data compressing/expanding mechanism in a multi-microprocessor environment Compressor/expander circuits which are built in a common semiconductor substrate along with a random access memory unit function so as to realize compression/expansion processes merely through the internal data transfer controls between the circuits and t... | 08/08/1995 |
| 5440709 | Apparatus and method for an improved content addressable memory using a random access memory to generate match information A content addressable memory, utilizing address recognition mechanism, comprising a Random Access Memory (RAM) including a plurality of data storage locations. Each of the data storage locations has a unique address. The content addressable memory operate... | 08/08/1995 |
| 5438665 | Direct memory access controller for handling cyclic execution of data transfer in accordance with stored transfer control information A direct memory access controller coupled to a system bus of a system for controlling data transfers through a channel includes the following. A request handler receives a transfer request generated by a device connected to the system bus. A transfer cont... | 08/01/1995 |
| 5434993 | Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus calle... | 07/18/1995 |
| 5430858 | Method for RAM conservation employing a RAM disk area non-sequential addresses on arranged order basis to access executable procedures A computer employs an operating system to perform a RAM conserving method that includes allocating a first portion of RAM for use as a RAM disk. The method comprises the steps of: storing an executable procedure comprising a plurality of sequentially exec... | 07/04/1995 |
| 5420996 | Data processing system having selective data save and address translation mechanism utilizing CPU idle period A main memory has a plurality of divided storage areas. A central processing unit saves data from each storage area of the main memory into an auxiliary memory during a normal operation of a computer system, and sets a flag corresponding to each storage a... | 05/30/1995 |
| 5412787 | Two-level TLB having the second level TLB implemented in cache tag RAMs A computer system implementing two levels of translation lookaside buffers (TLBs). The first-level TLBs are small, two-set associative, have a short access time and reside on the CPU chip. The second-level TLBs, on the other hand, are large, direct mapped... | 05/02/1995 |
| 5408629 | Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system A method and apparatus for granting exclusive access to a selected portion of addressable memory to a requesting processor in a large scale multiprocessor system. An instruction processor having a store-through operand cache executes an instruction requir... | 04/18/1995 |
| 5394535 | Memory access control circuit with automatic access mode determination circuitry with read-modify-write and write-per-bit operations A memory access control circuit determines an optimum memory access mode and performs the optimum memory access mode without requiring additional data from the data processing unit. The circuit performs a plurality of memory access operations, the number ... | 02/28/1995 |
| 5392417 | Processor cycle tracking in a controller for two-way set associative cache A processor communicates over a memory bus with a main memory and a cache by asserting an address strobe signal (ADS) to initiate a memory access. The cache includes a cache controller and a tag random access memory (tag RAM). Internal cycles are tracked ... | 02/21/1995 |
| 5383146 | Memory with CAM and RAM partitions A method is described of programming a memory array on a single integrated circuit so that a portion of each data word is characterized as CAM, with the remaining portion of each data word functioning as RAM. The programmable memory array is partitioned i... | 01/17/1995 |
| 5381539 | System and method for dynamically controlling cache management A cache management system and method monitors and controls the contents of cache memory coupled to at least one host and at least one data storage device. A cache indexer maintains a current index of data elements which are stored in cache memory. A seque... | 01/10/1995 |
| 5377345 | Methods and apparatus for providing multiple pending operations in a cache consistent multiple processor computer system Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the ... | 12/27/1994 |
| 5375219 | Common system with a plurality of processors using a common memory and utilizing an interrupt signal A plurality of processors and a particular processor use a common memory. A requesting processor requesting communication with the particular processor writes data at a predetermined address of the common memory which corresponds to the requesting process... | 12/20/1994 |
| 5375230 | Portable electronic device with selectable resume and suspend operations utilizing battery power control scheme with user affirmation prompt A portable electronic device comprises a control section comprising CPU and RAM which turn off a power if a keyboard has not been operated for a predetermined period of time, set whether the power is to be turned off, and set the predetermined period of t... | 12/20/1994 |
| 5371877 | Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory A circuit for providing the function of a dual port FIFO circuit including a first bank of single port random access memory, a second bank of single port random access memory, apparatus for sequentially writing every other piece of sequential data to an a... | 12/06/1994 |
| 5371865 | Computer with main memory and cache memory for employing array data pre-load operation utilizing base-address and offset operand A computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory and processing the data according to instructions. The pr... | 12/06/1994 |
| 5369753 | Method and apparatus for achieving multilevel inclusion in multilevel cache hierarchies A method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align on a "way" basis by their respective cache controllers communicating with each other which blocks of data they are replacing and which of... | 11/29/1994 |
| 5363496 | Microprocessor incorporating cache memory with selective purge operation A microprocessor incorporating a cache memory with a selective purge operation includes a control register for storing control information including page information for controlling a purge operation for purging a predetermined page divided in the cache m... | 11/08/1994 |
| 5363484 | Multiple computer system with combiner/memory interconnection system employing separate direct access link for transferring information packets A combiner/memory system interconnects a plurality of computer systems using for example the new HIPPI standard link. The combiner system includes it's own internal storage for rapid shared access to all connected computer systems. The combiner/memory sys... | 11/08/1994 |
| 5355461 | Method of and apparatus for selecting an origin address for use in translating a logical address in one of a plurality of virtual address spaces to a real address in a real address space A data processing system capable of accessing multiple virtual address spaces wherein a an access register translation is performed when obtaining an origin address (STO) of a translation table to be used for address translation of a logical address into ... | 10/11/1994 |
| 5349652 | Single chip integrated address manager with address translating unit An address manager, for use in a memory management system, translates a multiple-bit memory address received from a central processing unit and provides a translated memory address to a memory control unit. The address manager includes an address translat... | 09/20/1994 |
| 5345577 | Dram refresh controller with improved bus arbitration scheme A cache controller with both burst and hidden refresh modes. In the burst mode, refresh requests are counted, but not acted on, until a predetermined number of refresh requests have been received. At that time, multiple refreshes are done in a single sequ... | 09/06/1994 |
| 5345574 | Memory card having controller providing adjustable refresh to a plurality of DRAMs A dynamic access random access card is provided with a dynamic random access memory and a source for generating a plurality of reference clock pulses. A control circuit generates refresh operations of the dynamic access memory in response to the plurality... | 09/06/1994 |
| 5341494 | Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output ... | 08/23/1994 |
| 5339411 | Method for managing allocation of memory space A method of managing the memory space of a data processing device includes defining a number of memory blocks in the memory space and establishing a different maximum memory fragment size for each of the memory blocks. When a memory allocation request is ... | 08/16/1994 |
| 5339400 | Portable electronic device capable of selectively providing unused area size of whole memory or memory segments to external device A portable electronic device which can be connected to an external device comprises a memory, having a storage area of a predetermined storage capacity, for storing information, a CPU for controlling read/write access of information for the memory, a prog... | 08/16/1994 |
| 5333291 | Stride enhancer for high speed memory accesses with line fetching mode and normal mode employing boundary crossing determination A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride i... | 07/26/1994 |
| 5333292 | Microcomputer for selectively accessing non-volatile memory and other storage unit in response to allocated address inputs A microcomputer which is desired to be small and lightweight comprises an EPROM for storing an operation program for the microcomputer, a selection circuit which opens a gate connected to the ERPOM through the input of an address allocated to the EPROM, a... | 07/26/1994 |
| 5329633 | Cache memory system, and comparator and MOS analog XOR amplifier for use in the system The MOS analog multi-bit comparator amplifier for performing the high speed digital multi-bit comparator function which is required, for example, in Cache Tag Random Access Memory of a computer system, and to the MOS analog XOR amplifier for performing th... | 07/12/1994 |
