| Patent No. | Patent Title: |
| 5490260 | Solid-state RAM data storage for virtual memory computer using ... |
| 5481691 | Cache page replacement using sequential LIFO and non-sequential L... |
| 5465342 | Dynamically adaptive set associativity for cache memories |
| 5454099 | CPU implemented method for backing up modified data sets in non-v... |
| 5454091 | Virtual to physical address translation scheme with granularity h... |
| 5452420 | Intelligent network interface circuit for establishing communicat... |
| 5452423 | Two-ROM multibyte microcode address selection method and apparatu... |
| 5446856 | Circuitry and method for addressing global array elements in a ... |
| 5446854 | Virtual memory computer apparatus and address translation mechani... |
| 5442758 | Apparatus and method for achieving reduced overhead mutual exclus... |
| 5440718 | Single semiconductor substrate RAM device utilizing data com... |
| 5440709 | Apparatus and method for an improved content addressable memory u... |
| 5438665 | Direct memory access controller for handling cyclic execution of ... |
| 5434993 | Methods and apparatus for creating a pending write-back controlle... |
| 5430858 | Method for RAM conservation employing a RAM disk area non-sequent... |
| 5420996 | Data processing system having selective data save and address ... |
| 5412787 | Two-level TLB having the second level TLB implemented in cache ta... |
| 5408629 | Apparatus and method for controlling exclusive access to portions... |
| 5394535 | Memory access control circuit with automatic access mode determin... |
| 5392417 | Processor cycle tracking in a controller for two-way set associat... |
| 5383146 | Memory with CAM and RAM partitions |
| 5381539 | System and method for dynamically controlling cache management |
| 5377345 | Methods and apparatus for providing multiple pending operations i... |
| 5375219 | Common system with a plurality of processors using a common memor... |
| 5375230 | Portable electronic device with selectable resume and suspend ope... |
| 5371877 | Apparatus for alternatively accessing single port random access m... |
| 5371865 | Computer with main memory and cache memory for employing array da... |
| 5369753 | Method and apparatus for achieving multilevel inclusion in multil... |
| 5363496 | Microprocessor incorporating cache memory with selective purge op... |
| 5363484 | Multiple computer system with combiner/memory interconnection sys... |
| 5355461 | Method of and apparatus for selecting an origin address for use i... |
| 5349652 | Single chip integrated address manager with address translating u... |
| 5345577 | Dram refresh controller with improved bus arbitration scheme |
| 5345574 | Memory card having controller providing adjustable refresh to a ... |
| 5341494 | Memory accessing system with an interface and memory selection un... |
| 5339411 | Method for managing allocation of memory space |
| 5339400 | Portable electronic device capable of selectively providing unuse... |
| 5333291 | Stride enhancer for high speed memory accesses with line fetching... |
| 5333292 | Microcomputer for selectively accessing non-volatile memory and o... |
| 5329633 | Cache memory system, and comparator and MOS analog XOR amplifier ... |