Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 7462923 | Bipolar transistor formed using selective and non-selective epitaxy for base integration in a BiCMOS process According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitax... | 12/09/2008 |
| 7462865 | Display and manufacturing method thereof A display includes a substrate, a control electrode formed on the substrate, input and output electrodes formed on the substrate having facing sides facing each other with respect to the control electrode, a semiconductor layer contacting the input and the output el... | 12/09/2008 |
| 7456441 | Single well excess current dissipation circuit A current dissipation circuit that dissipates excess current to or from a circuit node when that monitored circuit node experiences abnormal voltage conditions, rather than having that excess current being dissipated through other protected circuitry. The current di... | 11/25/2008 |
| 7453109 | Solid-state image sensor and imaging system At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise. ... | 11/18/2008 |
| 7452771 | Method for fabricating a semiconductor device The semiconductor device comprises a first well 14 of a first conduction type formed in a semiconductor substrate 10; a second well 16 of a second conduction type formed in the first well 14; and a transistor 40 including a control... | 11/18/2008 |
| 7446370 | Non-volatile memory A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain regi... | 11/04/2008 |
| 7443006 | Photon amplification of image sensors A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer includes one or more rare earth elements for amplifying the number of photons capable of being converted t... | 10/28/2008 |
| 7442572 | CMOS image sensor and method for manufacturing the same A CMOS image sensor and a method for manufacturing the same improves photosensitivity and prevent loss of light by forming a photo-sensing unit under a color filter. The CMOS image sensor may include a plurality of transistors formed on a semiconductor substrate, a ... | 10/28/2008 |
| 7443090 | Surface-emission cathodes having cantilevered electrodes A surface-emission cathode formed on an insulating surface having cantilevered, i.e. “undercut,” electrodes. Suitable insulating surfaces include negative electron affinity (NEA) insulators such as glass or diamond. The cathode can operate in a comprised vacuum ... | 10/28/2008 |
| 7439592 | ESD protection for high voltage applications An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and ... | 10/21/2008 |
| 7439588 | Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, a... | 10/21/2008 |
| 7439608 | Symmetric bipolar junction transistor design for deep sub-micron fabrication processes Described herein are embodiments of a bipolar junction transistor including a plurality of base terminal rings having an emitter terminal ring between any two base terminal rings of the plurality of base terminal rings, and a collector terminal ring surrounding the ... | 10/21/2008 |
| 7436044 | Electrical fuses comprising thin film transistors (TFTS), and methods for programming same The present invention relates to electrical fuses that each comprises at least one thin film transistor. In one embodiment, the electrical fuse of the present invention comprises a hydrogenated thin film transistor with an adjacent heating element. Programming of su... | 10/14/2008 |
| 7432182 | Semiconductor device and method for manufacturing the same An exemplary method for manufacturing a semiconductor device includes: forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer, respectively formed thereabove and one or more junction regions formed therein so ... | 10/07/2008 |
| 7432153 | Direct tunneling semiconductor memory device and fabrication process thereof A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both ... | 10/07/2008 |
| 7425461 | Photon amplification for image sensors A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer includes one or more rare earth elements for amplifying the number of photons capable of being converted t... | 09/16/2008 |
| 7413937 | Semiconductor device A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film ... | 08/19/2008 |
| 7414289 | SOI Device with charging protection and methods of making same The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device i... | 08/19/2008 |
| 7414294 | Intermediate-band photosensitive device with quantum dots having tunneling barrier embedded in organic matrix A plurality of quantum dots each have a shell. The quantum dots are embedded in an organic matrix. At least the quantum dots and the organic matrix are photoconductive semiconductors. The shell of each quantum dot is arranged as a tunneling barrier to require a char... | 08/19/2008 |
| 7410823 | Image sensors for reducing dark current and methods of manufacturing the same An image sensor includes a substrate region of a first conductivity type, a photodiode region of a second conductivity type located in the substrate, a hole accumulated device (HAD) region of the first conductivity type located at a surface of the substrate and over... | 08/12/2008 |
| 7411265 | Photodiode and phototransistor A phototransistor includes a first-conduction-type lower region, a second-conduction-type upper region disposed on the first region, a second-conduction-type electrode contact region of a high concentration disposed at a surface inside of the upper region and is con... | 08/12/2008 |
| 7411230 | Solid-state imaging device and method of manufacturing said solid-state imaging device It is an object to provide solid-state imaging device, which can easily be manufactured and has a high reliability, and a method of manufacturing the solid-state imaging device. In the present invention, a manufacturing method comprises the steps of forming a plural... | 08/12/2008 |
| 7407818 | Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate, forming a lower electrode having a laminated film of Ir and IrO2 whose thickness is 100 nm or less over the semiconductor substrate, forming a cap... | 08/05/2008 |
| 7408211 | Transfer transistor of CMOS image sensor A transfer transistor of a CMOS image sensor is described, including a substrate of a first type, a gate dielectric layer on the substrate, a gate on the gate dielectric layer, a first doped region of the first type, a buried channel region of the first or second ty... | 08/05/2008 |
| 7405113 | Fabrication method of thin film transistor A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric la... | 07/29/2008 |
| 7405444 | Micro-mechanically strained semiconductor film A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process including performing a local oxidation of silicon (LOCOS) process in a substrate and removing resulting o... | 07/29/2008 |
| 7405446 | Electrostatic protection systems and methods Systems and methods are disclosed herein to provide improved electrostatic protection for electrical circuits. For example, in accordance with an embodiment of the present invention, an electrostatic protection device includes: a drain region formed in a substrate; ... | 07/29/2008 |
| 7405465 | Deposited semiconductor structure to minimize n-type dopant diffusion and method of making In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thic... | 07/29/2008 |
| 7402450 | Solid-state image pickup device A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed... | 07/22/2008 |
| 7402452 | Gate oxide film structure for a solid state image pick-up device In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by ... | 07/22/2008 |
| 7402866 | Backside contacts for MOS devices A semiconductor structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate dielectric over the first surface of the semiconductor substrate, a gate electrode over the gate dielectric, a source/drain re... | 07/22/2008 |
| 7402831 | Adapting short-wavelength LED's for polychromatic, broadband, or “white” emission An adapted LED is provided comprising a short-wavelength LED and a re-emitting semiconductor construction, wherein the re-emitting semiconductor construction comprises at least one potential well not located within a pn junction. The potential well(s) are typically ... | 07/22/2008 |
| 7402468 | Flat panel display and method of fabricating the same Disclosed is a flat panel display which comprises a substrate; a gate line formed on the substrate along a predetermined direction; and a gate electrode electrically connected to the gate line, and having a sheet resistance different from the gate line. With this co... | 07/22/2008 |
| 7400044 | Semiconductor integrated circuit device To improve a degree of integration and reliability of a semiconductor integrated circuit device. There are included third wire 14 arranged in the same layer as first wire 11 and second wire 12 and arranged in a direction intersecting with the fi... | 07/15/2008 |
| 7397088 | Electrostatic discharge protection device for radio frequency applications based on an isolated L-NPN device A lateral bipolar transistor is used to protect a passive radio frequency (RF) microelectronic circuit during electrostatic discharge (ESD) events. The microelectronic circuit receives a high frequency differential input signal across first and second pads. The late... | 07/08/2008 |
| 7397096 | Structure of sweep-type fingerprint sensing chip capable of resisting electrostatic discharge (ESD) and method of fabricating the same A structure of sweep-type fingerprint sensing chip capable of resisting electrostatic discharge (ESD) includes a semiconductor substrate, and a sweep-type fingerprint sensing chip formed on the semiconductor substrate, a polymer layer and a conducting metal layer. T... | 07/08/2008 |
| 7394126 | Non-volatile memory and manufacturing method thereof A non-volatile memory is described, including a substrate, a floating gate, a control gate, a source region, and a drain region. A trench is disposed in the substrate, and a step-like recess is located in the substrate beside the trench. The floating gate is dispose... | 07/01/2008 |
| 7394104 | Semiconductor optical device having current-confined structure Provided is a semiconductor optical device having a current-confined structure. The device includes a first semiconductor layer of a first conductivity type which is formed on a semiconductor substrate and includes one or more material layers, a second semiconductor... | 07/01/2008 |
| 7387907 | Image sensor with optical guard ring and fabrication method thereof An image sensor device and fabrication method thereof wherein a substrate having at least one shallow trench isolation structure therein is provided. At least one photosensor and at least one light emitting element, e.g., such as MOS or LED, are formed in the substr... | 06/17/2008 |
| 7385258 | Transistors having v-shape source/drain metal contacts A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor lay... | 06/10/2008 |
