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| Number | Title | Issue Date |
| 6900524 | Resin molded semiconductor device on a lead frame and method of manufacturing the same A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead port... | 05/31/2005 |
| 6888243 | Semiconductor device To improve the radiation property without inhibiting miniaturization of the device, heat generated at a heat generating layer (5) is radiated to a substrate (1) via plugs (7, 17), wiring layers (8, 18), and plugs (9, 19). A cross s... | 05/03/2005 |
| 6855575 | Semiconductor chip package having a semiconductor chip with center and edge bonding pads and manufacturing method thereof A method for manufacturing a semiconductor chip package includes: preparing a semiconductor chip having center and edge bonding pads and a substrate, which includes a first window, a second window, connection pads, external terminal pads, and a wiring pattern; attac... | 02/15/2005 |
| 6838767 | Semiconductor device Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the ... | 01/04/2005 |
| 6825547 | Semiconductor device including edge bond pads A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also inclu... | 11/30/2004 |
| 6803258 | Semiconductor device In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening... | 10/12/2004 |
| 6800942 | Vertically mountable semiconductor device and methods A vertically mountable semiconductor device including a plurality of bond pads disposed proximate to a single edge thereof. The bond pads are bumped with an electrically conductive material. The semiconductor device may also include a support member. Alternatively, ... | 10/05/2004 |
| 6791194 | Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an org... | 09/14/2004 |
| 6791185 | Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bum... | 09/14/2004 |
| 6787926 | Wire stitch bond on an integrated circuit bond pad and method of making the same A microelectronic assembly, and method of making the same, including a wire stitch bonded on an electroplated gold bump or electroless nickel/gold bump on a bond pad of an integrated circuit chip. The electroplated gold bump or electroless nickel/gold bump provides ... | 09/07/2004 |
| 6787897 | Wafer-level package with silicon gasket A gasket encloses a hermetically sealed environment between a cap wafer and a base wafer. The gasket is bonded to the base wafer using bonding material. The bonding material can be one or more of many substances that exhibit acceptable adhesion, sealing, and other p... | 09/07/2004 |
| 6784534 | Thin integrated circuit package having an optically transparent window A thin integrated circuit package having an optically transparent window provides a small profile optical integrated circuit assembly for use in digital cameras, video cellular telephones and other devices requiring a small physical size and optical integrated circu... | 08/31/2004 |
| 6770980 | Semiconductor device having semiconductor element packaged on interposer First electrodes disposed on the surface of the substrate comprise a plurality of chip select electrodes, and the first chip select electrode among a plurality of chip select electrodes to in electrically connected only to a semiconductor element. The N-th (N is a i... | 08/03/2004 |
| 6765720 | Glass microspheres for use in films and projection screen displays Glass microspheres and rear projection screens containing glass microspheres, which combine a desirable index of refraction (preferably, no greater than about 1.70) and low levels of defects (e.g., bubbles, visible haziness, frostiness, or opacity, substantially non... | 07/20/2004 |
| 6762505 | 150 degree bump placement layout for an integrated circuit power grid A 150 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Fu... | 07/13/2004 |
| 6753556 | Silicate gate dielectric A method of forming a silicate dielectric having superior electrical properties comprising forming a metal oxide layer on a Si-containing semiconductor material and reacting the metal oxide with the underlying Si-containing material in the presence of an oxidizing g... | 06/22/2004 |
| 6744121 | Multi-chip package A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead from inside to outside being divided into a first inner portion, a supporting portion, a second inner portion and an outer connecting portion. By ... | 06/01/2004 |
| 6734555 | Integrated circuit package and printed circuit board arrangement An integrated circuit package device (100, 200, 300) has a plurality of contact points including an inner portion of contact points (120) and an outer portion of contact points (110). The integrated circuit package device includes at least one o... | 05/11/2004 |
| 6727582 | Semiconductor device A semiconductor device formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semicond... | 04/27/2004 |
| 6716673 | Two-pole SMT miniature housing for semiconductor components and method for the manufacture thereof In a two-pole SMT miniature housing in leadframe technique for semiconductor components, a semiconductor chip is mounted on one leadframe part and is contacted to a further leadframe part. The further leadframe part is conducted out of the housing in which the chip ... | 04/06/2004 |
| 6717255 | Chip carrier for a high-frequency electronic package An electronic package is provided. The electronic package includes a chip carrier having a first conductive layer which includes at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted fo... | 04/06/2004 |
| 6717279 | Semiconductor device with recessed portion in the molding resin A semiconductor device can perform resin sealing of an under-fill region and peripheral portion on the side of a semiconductor chip in the same process step, with shortening periods required for filling and curing the under-fill resin and avoiding formation of an in... | 04/06/2004 |
| 6713815 | Semiconductor device with transistors that convert a voltage difference into a drain current difference A semiconductor device is provided, which includes a pair of differential transistors that convert a voltage difference between a first input terminal and a second input terminal into a drain current difference between a first transistor and a second transistor and ... | 03/30/2004 |
| 6713792 | Integrated circuit heat sink device including through hole to facilitate communication A method of manufacturing a printed circuit board through-hole connection includes forming a through-hole by removing material from the first side of the printed circuit board until the backing and then slightly into the first side of the backing providing a hole. N... | 03/30/2004 |
| 6713862 | Low temperature co-fired ceramic-metal packaging technology Integrated packages incorporating multilayer ceramic circuit boards mounted on a metal support substrate can be used for temperature control by the metal support substrate. Various electronic components, as well as additional temperature control devices, can be conn... | 03/30/2004 |
| 6713844 | Semiconductor-chip mounting substrate having at least one projection thereon and a pressure holding means A semiconductor-chip mounting substrate with a high degree of reliability of an electrical connection between a substrate and a semiconductor chip such as IC chips is provided. The substrate has at least one projection thereon, which is integrally molded with the su... | 03/30/2004 |
| 6710433 | Leadless chip carrier with embedded inductor One embodiment comprises a substrate having a top surface for receiving a semiconductor die. According to a disclosed embodiment, an inductor is patterned on the top surface of the substrate. The inductor is easily accessible by connecting its first and second termi... | 03/23/2004 |
| 6710446 | Semiconductor device comprising stress relaxation layers and method for manufacturing the same A semiconductor device and a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the semiconductor elemen... | 03/23/2004 |
| 6707139 | Semiconductor device with plural unit regions in which one or more MOSFETs are formed A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the... | 03/16/2004 |
| 6707148 | Bumped integrated circuits for optical applications An optical integrated circuit application where the integrated circuit is packaged in a clear molding material and is attached to a printed circuit board having an aperture is described. The integrated circuit senses and/or emits light through the clear molding mate... | 03/16/2004 |
| 6707149 | Low cost and compliant microelectronic packages for high i/o and fine pitch A method of making a compliant microelectronic package includes providing a first substrate having a top surface with conductive pads and an opening extending therethrough to the first substrate so that a bottom surface of the second substrate confronts a top surfac... | 03/16/2004 |
| 6707168 | Shielded semiconductor package with single-sided substrate and method for making the same A semiconductor chip package is disclosed. The package includes a substrate, a metallization layer formed on one side of the substrate and a semiconductor die mounted on the substrate. The semiconductor die is electrically connected to a portion of the metallization... | 03/16/2004 |
| 6707153 | Semiconductor chip with plural resin layers on a surface thereof and method of manufacturing same A method of manufacturing a semiconductor device comprising a step of forming a plurality of resin layers, an interconnect connected electrically to an electrode of each of a plurality of semiconductor elements, and an external terminal connected electrically to the... | 03/16/2004 |
| 6707167 | Semiconductor package with crack-preventing member A semiconductor package with a crack-preventing member is proposed, in which a chip is mounted on a chip carrier by means of an adhesive and is electrically connected to the chip carrier. The crack-preventing member is formed at a proper position on the chip, and ge... | 03/16/2004 |
| 6703701 | Semiconductor device with integrated circuit elements of group III-V comprising means for preventing pollution by hydrogen A semiconductor device comprising integrated circuit elements realized by means of a stack of layers of semiconductor materials provided on a substrate of semiconductor material and comprising means for preventing the pollution of the circuit elements and... | 03/09/2004 |
| 6700203 | Semiconductor structure having in-situ formed unit resistors An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an ins... | 03/02/2004 |
| 6700207 | Flip-chip ball grid array package for electromigration testing A test package for electromigration testing includes a die having a plurality of I/O pads formed on a metal layer, a plurality of traces formed on the die electrically connecting adjacent pairs of the I/O pads, a plurality of bumped interconnects formed o... | 03/02/2004 |
| 6700162 | Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The f... | 03/02/2004 |
| 6700178 | Package of a chip with beveled edges A chip with beveled edges suitable for adhering onto a surface of a die pad by an adhesive material. The chip has an active surface and a corresponding back surface, wherein the active surface has beveled edges. The back surface of the chip is adhered ont... | 03/02/2004 |
| 6700200 | Reliable via structures having hydrophobic inner wall surfaces Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a l... | 03/02/2004 |
