| Patent No. | Patent Title: |
| 6979580 | Process for controlling performance characteristics of a negative... |
| 6962882 | Method of fabricating a semiconductor device having a nanoparticl... |
| 6943127 | CVD plasma assisted lower dielectric constant SICOH film |
| 6900144 | Film-forming surface reforming method and semiconductor device ma... |
| 6887724 | Test element group, method of manufacturing a test element group,... |
| 6887749 | Multiple oxide thicknesses for merged memory and logic applicatio... |
| 6884740 | Photoelectrochemical undercut etching of semiconductor material |
| 6875692 | Copper electromigration inhibition by copper alloy formation |
| 6855581 | Method for fabricating a high-voltage high-power integrated circu... |
| 6855642 | Method for fabricating semiconductor integrated circuit device |
| 6852650 | Insulation film on semiconductor substrate and method for forming... |
| 6849483 | Charge trapping device and method of forming the same |
| 6849518 | Dual trench isolation using single critical lithographic patterni... |
| 6846730 | Two stage etching of silicon nitride to form a nitride spacer |
| 6846699 | Semiconductor device and method of manufacture thereof, circuit b... |
| 6841487 | Method of manufacturing semiconductor device and flash memory |
| 6841404 | Method for determining optical constant of antireflective layer, ... |
| 6835671 | Method of making an integrated circuit using an EUV mask formed b... |
| 6835668 | Copper post-etch cleaning process |
| 6835659 | Electrical coupling stack and processes for making same |
| 6835660 | Method of manufacturing semiconductor device having metal alloy i... |
| 6833331 | Method of manufacturing semiconductor integrated circuit device h... |
| 6828201 | Method of manufacturing a top insulating layer for a sonos-type d... |
| 6828196 | Trench filling process for preventing formation of voids in trenc... |
| 6825120 | Metal surface and film protection method to prolong Q-time after ... |
| 6825072 | Method of manufacturing a semiconductor device |
| 6818525 | Semiconductor device and method of providing regions of low subst... |
| 6818481 | Method to manufacture a buried electrode PCRAM cell |
| 6818553 | Etching process for high-k gate dielectrics |
| 6812084 | Adaptive negative differential resistance device |
| 6812167 | Method for improving adhesion between dielectric material layers |
| 6808957 | Method for improving a high-speed edge-coupled photodetector |
| 6808942 | Method for controlling a critical dimension (CD) in an etch proce... |
| 6806117 | Methods of testing/stressing a charge trapping device |
| 6803297 | Optimal spike anneal ambient |
| 6800940 | Low k dielectric composite layer for integrated circuit structure... |
| 6800927 | Multiple oxide thicknesses for merged memory and logic applicatio... |
| 6797615 | Method of manufacturing a semiconductor device |
| 6797652 | Copper damascene with low-k capping layer and improved electromig... |
| 6797644 | Method to reduce charge interface traps and channel hot carrier d... |
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