U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

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Examiner: Garbowski, Leigh Marie


Primary examiner statistics: 551 patents; average approval time: 551 days
Assistant examiner statistics: 354 patents; average approval time: 942 days

Patents as Primary Examiner (view all)

Patent No. Patent Title:
8060847 Clock model for formal verification of a digital circuit descript...
8020120 Layout quality gauge for integrated circuit design
8020132 Combined memories in integrated circuits
8015527 Routing of wires of an electronic circuit
8010922 Automated method for buffering in a VLSI design
8006213 Optimization method of integrated circuit design for reduction of...
8001492 Evaluation method for interconnects interacted with integrated-ci...
8001515 Simultaneous optimization of analog design parameters using a cos...
8001508 Method and system for analyzing input/output simultaneous switchi...
7987439 Method and apparatus for analyzing circuit model by reduction and...
7987434 Calculation system for inverse masks
7987435 Pattern verification method, program thereof, and manufacturing m...
7984406 Timing verification method and apparatus
7984395 Hierarchical compression for metal one logic layer
7979834 Predicting timing degradations for data signals in an integrated ...
7979835 Method of estimating resource requirements for a circuit design
7975253 Power supply noise analysis model generating method and power sup...
7971163 Property generating apparatus, property generating method and pro...
7971177 Design tool for charge trapping memory using simulated programmin...
7966586 Intelligent pattern signature based on lithography effects
7966593 Integrated circuit design system, method, and computer program pr...
7966582 Method and apparatus for modeling long-range EUVL flare
7966584 Pattern-producing method for semiconductor device
7958475 Synthesis of assertions from statements of power intent
7958484 Affinity-based clustering of vectors for partitioning the columns...
7945890 Registry for electronic design automation of integrated circuits
7930657 Methods of forming photomasks
7930665 Method and program for designing semiconductor integrated circuit
7921404 Method of reusing constraints in PCB designs
7921391 Apparatus, method and computer-readable code for automated design...
7917879 Semiconductor device with dynamic array section
7908573 Minimizing effects of interconnect variations in integrated circu...
7904865 Placement driven routing
7904871 Computer-implemented method of optimizing refraction and TIR stru...
7900182 Method and system for designing an electronic circuit
7900171 Electronic stream processing circuit with locally controlled para...
7900174 Method and system for characterizing an integrated circuit design
7890892 Balanced and bi-directional bit line paths for memory arrays with...
7882466 Noise checking method and apparatus, and computer-readable record...
7877718 Analog IC placement using symmetry-islands

Patents as Assistant Examiner (view all)

Patent No. Patent Title:
6658634 Logic power optimization algorithm
6604231 Three-dimensional MCM, method for manufacturing the same, and sto...
6584601 System and method for converting graphical programs into hardware...
6571383 Semiconductor device fabrication using a photomask designed using...
6553543 Automated load determination for partitioned simulation
6539519 Spatial characteristic and logical hierarchy based manner for com...
6539521 Dissection of corners in a fabrication layout for correcting prox...
6536023 Method and system for hierarchical metal-end, enclosure and expos...
6526558 Methods for configuring FPGA's having variable grain blocks and s...
6507941 Subgrid detailed routing
6505339 Behavioral synthesis links to logic synthesis
6496958 Yield prediction and statistical process control using predicted ...
6496965 Automated design of parallel drive standard cells
6493866 Phase-shift lithography mapping and apparatus
6490717 Generation of sub-netlists for use in incremental compilation
6484291 Library for storing pattern shape of connecting terminal and semi...
6477692 Method and apparatus for channel-routing of an electronic device
6467076 Method and apparatus for submicron IC design
6460164 Integration of externally developed logic in a memory mapped syst...
6457169 Geometric phase analysis for overlay measurement
6449759 System and method for automatic insertion and placement of repeat...
6449748 Non-destructive method of detecting die crack problems
6449761 Method and apparatus for providing multiple electronic design sol...
6449749 System and method for product yield prediction
6442739 System and method for timing abstraction of digital logic circuit...
6442747 Method of synthesizing a cycle redundancy code generator circuit ...
6438729 Connectivity-based approach for extracting layout parasitics
6430733 Contextual based groundrule compensation method of mask data set ...
6425113 Integrated verification and manufacturability tool
6421814 Method of extracting layout parasitics for nets of an integrated ...
6421812 Programming mode selection with JTAG circuits
6415432 Lithography pattern data generation method, lithography pattern f...
6415421 Integrated verification and manufacturability tool
6412100 Method for solving a layout optimization problem, and computer-re...
6408427 Wire width planning and performance optimization for VLSI interco...
6401235 Method of and apparatus for producing exposure mask
6393602 Method of a comprehensive sequential analysis of the yield losses...
6389584 Gate input protection with a reduced number of antenna diodes
6385760 System and method for concurrent placement of gates and associate...
6381731 Placement based design cells injection into an integrated circuit...
 
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