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| Number | Title | Issue Date |
| 6034550 | Multi-power IC device A multiple-power IC device comprising an input buffer circuit for receiving an input signal and a plurality of power voltages of different magnitudes. The input buffer circuit has an output associated with each of the plurality of power voltages for outpu... | 03/07/2000 |
| 6034548 | Programmable delay element The invention provides a programmable delay element and a programmable slew rate element to allow post-fabrication adjustment and programming of input delay and output slew rate to iteratively alter input delay and output slew rate without redesign and re... | 03/07/2000 |
| 6034546 | High performance product term based carry chain scheme A macrocell for a programmable logic device includes a carry generator for generating a carry input to the macrocell, the carry generator having an inverting input and at least one non-inverting input. A carry decoupler controls the carry generator and al... | 03/07/2000 |
| 6034545 | Macrocell for data processing circuit The present invention provides a macrocell for a data processing circuit, comprising macrocell logic, and an interface for connecting the macrocell logic to a bus of the data processing circuit. The interface comprises: an input bus connected to an input ... | 03/07/2000 |
| 6031396 | Circuit for synchronizing asynchronous inputs using dual edge logic design A synchronizing circuit processes a plurality (N) of input signals to generate a synchronizing circuit output signal, and provides the synchronizing circuit output signal synchronous to a system clock, wherein the N input signals are asynchronous to the s... | 02/29/2000 |
| 6031389 | Slew rate limited output driver A slew-rate limited output driver circuit that minimizes switching current while delivering sufficient peak load currents is disclosed. The circuit of the present invention includes fixed pull-up and pull-down transistors that are designed to dissipate mi... | 02/29/2000 |
| 6028451 | Method and apparatus for topology dependent slew rate control A slew rate control circuit of a bus includes two connection devices that are adapted to be coupled to two voltage supplies. The connection devices are connected to the bus by a select terminal of a signal application device. The signal application device... | 02/22/2000 |
| 6028444 | Three-statable net driver for antifuse field programmable gate array Internal net drivers of a field programmable gate array are laid out with additional transistors to increase current drive capability at low supply voltages when a low supply voltage mask option is used. When a high supply voltage mask option is used, the... | 02/22/2000 |
| 6028454 | Dynamic current mode logic family A dynamic current mode circuit for low-voltage and high performance VLSI applications, comprising a MOS current mode logic block and dynamic circuitry for precharging the outputs of the MOS current mode logic block, cross-coupled latches for enhancing per... | 02/22/2000 |
| 6028452 | Method and apparatus for a fast variable precedence priority encoder with optimized round robin precedence update scheme A variable precedence priority encoder apparatus is provided having a plurality of inputs, each receiving a corresponding bit of an input vector, and a like plurality of outputs. Each output is associated with a corresponding one of the plurality of input... | 02/22/2000 |
| 6025747 | Logic signal selection circuit It is to achieve a logic signal selection circuit having high timing resolution and high speed. The logic signal selection circuit includes a current input type sense amplifier 320 which is provided with a threshold value which is an output of an equivale... | 02/15/2000 |
| 6025738 | Gain enhanced split drive buffer A system and method for increasing the gain per stage and signal edge transition speed, as well as the edge phase accuracy of an input signal. In an exemplary embodiment, a distributed clock signal is produced by an enhanced clock buffer circuit which inc... | 02/15/2000 |
| 6023175 | Level interface circuit The present invention relates to a level interface circuit, which receives a first interface input signal having a level H and a level L, as fixed potentials, and a first reference level which is midway therebetween, and a second interface input signals h... | 02/08/2000 |
| 6020764 | Emitter coupled logic circuitry with additional discharge path There is provided emitter coupled logic (ECL) circuitry comprising a differential amplifier circuit for receiving an input signal and a reference potential Vbb, and for causing an output circuit to make a transition to its high state by charging a parasit... | 02/01/2000 |
| 6020761 | Input buffers and controlling methods for integrated circuit memory devices that operate with low voltage transistor-transistor logic (LVTTL) and with stub series terminated transceiver logic (SSTL) An input buffer that can operate with Low Voltage Transistor-Transistor Logic (LVTTL) and with Stub Series Terminated transceiver Logic (SSTL) includes a differential amplifier that differentially amplifies a reference voltage and an external input signal... | 02/01/2000 |
| 6020763 | High speed decoder without race condition A self-clocked apparatus for eliminating race condition in high speed decoders is provided. In multi-stage decoders, a first stage is generally composed of predecoder blocks while a second stage is generally composed of decoder/driver blocks. Each predeco... | 02/01/2000 |
| 6020762 | Digital voltage translator and its method of operation A signal translator circuit for particular use with low level logic signals is designed to accept a low level transitioning signal in a lower voltage range and output a signal transitioning within a higher voltage range. Circuitry is provided to ensure pr... | 02/01/2000 |
| 6018251 | Programmable integrated circuit having parallel routing conductors coupled to programming drivers in different locations A programmable integrated circuit (see FIG. 18) includes a plurality of interface cells with programmable antifuses disposed on a branch of a routing conductor. The routing conductor extends in a first direction and is coupled to one terminal of a program... | 01/25/2000 |
| 6018255 | Line decoder for memory devices The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage include... | 01/25/2000 |
| 6018254 | Non-blocking delayed clocking system for domino logic A non-blocking multiple-phase clocking system for use with domino-type dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that i... | 01/25/2000 |
| 6016065 | Charges recycling differential logic(CRDL) circuit and storage elements and devices using the same A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at a same signal level of a previous state when an input sig... | 01/18/2000 |
| 6014037 | Method and component arrangement for enhancing signal integrity Embodiments of the invention include a method and arrangement of integrated circuit components for enhancing the integrity of communication signals transmitted through a multi-device communication system. Embodiments of the invention provide controllable ... | 01/11/2000 |
| 6014039 | CMOS high voltage drive output buffer A CMOS high voltage drive output buffer that protects the drive stage from seeing relatively high voltages (e.g., 5 V) during "hot pluggable" conditions (that is, when the reference voltage VDD is not present). A transmission gate and clamping transistors... | 01/11/2000 |
| 6011407 | Field programmable gate array with dedicated computer bus interface and method for configuring both A field programmable gate array is provided which has a programmable portion and a dedicated controller-interface circuit. The programmable portion includes conventional input/output (I/O) blocks and configurable logic blocks (CLBs). The controller-interf... | 01/04/2000 |
| 6011408 | Programmable integrated circuit having a routing conductor that is driven with programming current from two different programming voltage terminals A programmable integrated circuit (see FIG. 10) includes a routing conductor, i.e., "express wire," that extends substantially across the array of the integrated circuit. Because of the metal resistance through the long express wire, the express wire is s... | 01/04/2000 |
| 6005417 | Method and apparatus for reducing power consumption in a domino logic by reducing unnecessary toggles A method and apparatus for reducing power consumption in a domino logic is provided. An input of the domino logic block has as an output of an upstream logic block. A first state, e.g. default or idle, of the output of the upstream logic block is determin... | 12/21/1999 |
| 6005412 | AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip An I/O interface includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications. Three clock tree... | 12/21/1999 |
| 6005414 | Mixed-mode multi-protocol serial interface driver A mixed-mode multi-protocol serial interface driver is presented. The driver operates in current-mode, voltage-mode, or both, and includes circuitry for conforming output signals to one of a plurality of selectable electrical interface standards, includin... | 12/21/1999 |
| 6002271 | Dynamic MOS logic circuit without charge sharing noise Circuitry for eliminating charge sharing noise in MOS dynamic logic circuits is described. Dynamic logic circuits having stacks of MOS devices controlling the state of a common node defining the output logic state of the circuit are susceptible to charge ... | 12/14/1999 |
| 5999018 | Programmable buffer circuit comprising reduced number of transistors A programmable buffer circuit includes a first stage circuit which receives an input signal IN indicative of a first or second value, and a second stage circuit, responsive to an output of the first stage circuit, for outputting one of a value designated ... | 12/07/1999 |
| 5994925 | Pseudo-differential logic receiver A pseudo-differential receiver is described which includes a bias generator circuit portion for providing a bias signal to a receiver circuit portion. The bias generator includes first and second load devices for establishing bias voltages at first and se... | 11/30/1999 |
| 5994924 | Clock distribution network with dual wire routing A new clock distribution network design for VLSI circuits which effectively reduces skew without the area and power penalty associated with prior clock designs. Two wires emanating from the clock in opposite directions or, alternatively, two wires connect... | 11/30/1999 |
| 5994922 | Output buffer, semiconductor integrated circuit having output buffer and driving ability adjusting method for output buffer A semiconductor integrated circuit has an internal circuit to execute a predetermined circuit operation, an input node to which output from the internal circuit is provided, and an output buffer capable of changing its driving ability placed between the i... | 11/30/1999 |
| 5990705 | CMOS I/O circuit with high-voltage input tolerance The invention provides for an input/output circuit in a CMOS integrated circuit which can withstand pad voltages which are higher than the supply voltages for the integrated circuit. The input/output circuit has a pair of first polarity-type transistors w... | 11/23/1999 |
| 5990706 | Logic circuit and method of designing the same A CMOS logic circuit consists of a domino gate serving as a logic gate 1 not disposed on a critical path and operating on a lower supply voltage (VDDL) and another domino gate serving as a logic gate 2 operating on a higher supply voltage (VDDH). An outpu... | 11/23/1999 |
| 5986472 | Voltage level translation for an output driver system with a bias generator Circuit and method aspects are provided for voltage level translation circuit for an output driver. In a circuit aspect, a circuit includes an input mechanism for receiving an internal data signal of a first predetermined voltage range, at least two stack... | 11/16/1999 |
| 5986469 | Programmable integrated circuit having L-shaped programming power buses that extend along sides of the integrated circuit A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each L-shaped programming power bus extends along two adjacent sides... | 11/16/1999 |
| 5986465 | Programmable logic integrated circuit architecture incorporating a global shareable expander A logic element for a programmable logic device to implement a global shareable expander. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element... | 11/16/1999 |
| 5986464 | Threshold logic circuit with low space requirement A threshold logic circuit with a low space requirement includes a first and at least one second circuit portion, each of which has an evaluator circuit and at least two branches to be evaluated. A partial sum signal formed in the first circuit portion is ... | 11/16/1999 |
| 5986463 | Differential signal generating circuit having current spike suppressing circuit The different signal generation circuit has a first transistor MP2 connected between a first power supply line Vcc and a first output terminal OTP and a gate connected to a first node, a second transistor MN2 connected between the first output terminal OT... | 11/16/1999 |
