Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| RE41310 | Methods for growing semiconductors and devices thereof the alloy semiconductor gainnas A method is disclosed for growing a nitrogen-containing III-V alloy semiconductor on a semiconductor substrate such as GaAs, which is formed by MOCVD method using nitrogen containing organic compounds having relatively low dissociation temperatures. The alloy semico... | 05/04/2010 |
| 7057257 | Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 06/06/2006 |
| 6890842 | Method of forming a thin film transistor A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adja... | 05/10/2005 |
| 6891209 | Dynamic random access memory trench capacitors DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined. ... | 05/10/2005 |
| 6875646 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 04/05/2005 |
| 6867068 | Semiconductor device, method of making the same, circuit board, and film carrier tape This is a semiconductor device made by using a film carrier tape and method of making the same, wherein the package size is close to the chip size and connection portions for electrodes of a semiconductor chip are not exposed. Electroplating is performed in a state ... | 03/15/2005 |
| 6861731 | Module and electronic device A radio module (10) suitable for RF applications, especially for Bluetooth, comprises a substrate (1) with a semiconductor device (11), a shield (21), and an antenna (31). The shield (21) is located between the antenna (3... | 03/01/2005 |
| 6838734 | ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications High-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process were activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (... | 01/04/2005 |
| 6831324 | Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by the same A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process. ... | 12/14/2004 |
| 6830940 | Method and apparatus for performing whole wafer burn-in A method and apparatus for burning in a semiconductor wafer having a plurality of active devices utilizes temporary conductive interconnect layers to separately couple at least a portion of the anodes of the active devices together as well as at least a portion of t... | 12/14/2004 |
| 6830976 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. ... | 12/14/2004 |
| 6825488 | Semiconductor device and manufacturing method thereof The aperture ratio of a pixel of a reflecting type display device is improved without increasing the number of masks and without using a black mask. Locations for light shielding between pixels are arranged such that a pixel electrode overlaps with a portion of a ga... | 11/30/2004 |
| 6821909 | Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a f... | 11/23/2004 |
| 6818535 | Thin phosphorus nitride film as an n-type doping source used in a laser doping technology An improved method and system for laser doping a semiconductor material is described. In the invention, phosphorous nitride is used as a dopant source. The phosphorous nitride is brought into close proximity with a region of the semiconductor to be doped. A pulse of... | 11/16/2004 |
| 6818536 | Semiconductor device and method of manufacturing the same A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region... | 11/16/2004 |
| 6815354 | Method and structure for thru-mask contact electrodeposition A process for forming a conductive structure on a substrate is provided. The substrate has a copper seed layer that is partially exposed through a plurality of openings in a masking layer such as a photoresist. The masking layer is formed on the seed layer. The proc... | 11/09/2004 |
| 6808951 | Semiconductor integrated circuit device and manufacturing method thereof An insulating film for protecting an upper portion of a control gate electrode is constituted by a silicon oxide film, and thereby stress affecting a gate oxide film and a substrate that is located below a bottom portion thereof is reduced. Further, an etching preve... | 10/26/2004 |
| 6809044 | Method for making a thin film using pressurization The invention relates to a process for making a thin film starting from a substrate (1) of a solid material with a plane face (2) comprising: the implantation of gaseous compounds in the substrate (1) to make a... | 10/26/2004 |
| 6809028 | Chemistry for liner removal in a dual damascene process An improved and new process for fabricating dual damascene copper, in which trench/via liner removal from porous low-k dielectric, is performed using a new RIE chemistry of CF4/H2, to etch SiN and SiC liners. Prior to the new process, conventio... | 10/26/2004 |
| 6806169 | Semiconductor device manufacturing method In a manufacturing method of a thin-film transistor having a polycrystalline Si film as its active region, an amorphous-phase Si film is first formed, and pulse laser beams are irradiated to crystallize the Si film and thereby form a polycrystalline Si film. After e... | 10/19/2004 |
| 6798071 | Semiconductor integrated circuit device In a semiconductor IC device, a first IC chip having a plurality of first electrodes and a second IC chip having a plurality of second electrodes are stacked. A plurality of relay electrodes are provided on the first IC chip. The first electrodes are electrically co... | 09/28/2004 |
| 6794261 | Methods of forming void regions, dielectric regions and capacitor constructions In one aspect, the invention includes a method of forming a void region associated with a substrate, comprising: a) providing a substrate; b) forming a sacrificial mass over the substrate; c) subjecting the mass to hydrogen to convert a component of the mass to a vo... | 09/21/2004 |
| 6794264 | Implantation process using substoichiometric, oxygen doses at different energies The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of i... | 09/21/2004 |
| 6784037 | Semiconductor device and manufacturing method therefor An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions incr... | 08/31/2004 |
| 6780726 | Scratch protection for direct contact sensors In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passiv... | 08/24/2004 |
| 6765231 | Semiconductor device and its manufacturing method An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel portion, a scanning line (gate line) and a data line are suitably arranged, and high numerical aperture is reali... | 07/20/2004 |
| 6762091 | Methods for manufacturing semiconductor devices having a metal layer Methods are provided for manufacturing an integrated circuit device in which a metal layer is formed on an integrated circuit substrate. A capping layer is formed on the metal layer opposite the integrated circuit substrate. The metal layer covered with the capping ... | 07/13/2004 |
| 6759308 | Silicon on insulator field effect transistor with heterojunction gate A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. Th... | 07/06/2004 |
| 6756242 | Method of modifying an integrated circuit The invention provides a method of modifying an integrated circuit, the method including the steps of selecting a scaling factor (72), scaling the circuit (74) according to the scaling factor, and adjusting the circuit for functionality and design rule... | 06/29/2004 |
| 6756273 | Semiconductor component and method of manufacturing A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component als... | 06/29/2004 |
| 6746942 | SEMICONDUCTOR THIN FILM AND METHOD OF FABRICATING SEMICONDUCTOR THIN FILM, APPARATUS FOR FABRICATING SINGLE CRYSTAL SEMICONDUCTOR THIN FILM, AND METHOD OF FABRICATING SINGLE CRYSTAL THIN FILM, SINGLE CRYSTAL THIN FILM SUBSTRATE, AND SEMICONDUCTOR DEVICE A method of fabricating a single crystal thin film includes: forming a non-single crystal thin film on an insulating base; subjecting the non-single crystal thin film to a first heat-treatment, thereby forming a polycrystalline thin film in which polycrystalline gra... | 06/08/2004 |
| 6743664 | Flip-chip on flex for high performance packaging applications A method is provided including attaching an encapsulant to an integrated circuit (IC), forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, attaching a first surface of the substrate to the encapsulan... | 06/01/2004 |
| 6740595 | Etch process for recessing polysilicon in trench structures A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon. ... | 05/25/2004 |
| 6740929 | Semiconductor device and method for testing semiconductor device A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated.... | 05/25/2004 |
| 6737304 | Process of fabricating a semiconductor device A semiconductor device having high operating performance and reliability is disclosed, and its fabrication process is also disclosed. In an n-channel type TFT 302, an Lov region 207 is disposed, whereby a TFT structure highly resistant to hot ca... | 05/18/2004 |
| 6737699 | Enhanced on-chip decoupling capacitors and method of making same An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method incl... | 05/18/2004 |
| 6730560 | Method for fabricating semiconductor device First, a capacitor device including a capacitor dielectric film of a metal oxide is formed on a substrate. Subsequently, an interlayer insulating film of an oxide is deposited on the capacitor device, an opening is formed in a region of the interlayer insulating fil... | 05/04/2004 |
| 6730581 | Semiconductor device and method of manufacture thereof Variations in threshold voltage among MOS devices are prevented by forming a metal gate electrode having an average grain size of 30 nm or less on a gate insulating film. ... | 05/04/2004 |
| 6727561 | Surface shape recognition sensor and method of manufacturing the same A surface shape recognition sensor includes a plurality of capacitive detection elements, a support electrode, and a protective film. The capacitive detection elements are formed from lower electrodes and a deformable plate-like upper electrode made of a metal. The ... | 04/27/2004 |
| 6727149 | Method of making a hybrid SOI device that suppresses floating body effects A method of making a Silicon-on-Insulator (SOI) transistor includes forming a body layer that is fully depleted when the SOI transistor is in a conductive state and forming first p+ regions adjacent each of the SOI transistor source/drain regions to adjus... | 04/27/2004 |
