Did You Know...
...that it was melting ice cream that inspired the invention of the outboard motor? It was a lovely August day and Ole Evinrude was rowing his boat to his favorite island picnic spot. As he rowed, he watched his ice cream melt and wished he had a faster way to get to the island. At that moment the idea for the outboard motor was born!
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| Number | Title | Issue Date |
| 8117427 | Motherboard, storage device and controller thereof, and booting method A motherboard, a storage device and a controller thereof and a booting method are provided. In the present invention, when powered on, an unfetch signal is transmitted to a central processor unit (CPU) by a controller such that an operation of the CPU is suspended. ... | 02/14/2012 |
| 8112618 | Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130 | 02/07/2012 |
| 8112641 | Facilitating communication and power transfer between electrically-isolated powered device subsystems A system employing power over Ethernet (PoE) technology may include at least one powered device and power sourcing equipment (PSE). The powered device may include a first powered device (PD) subsystem and a second powered device (PD) subsystem that is electrically i... | 02/07/2012 |
| 8112654 | Method and an apparatus for providing timing signals to a number of circuits, and integrated circuit and a node A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal befo... | 02/07/2012 |
| 8108708 | Power optimization when using external clock sources Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be pro... | 01/31/2012 |
| 8108664 | Fast and compact circuit for bus inversion A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, t... | 01/31/2012 |
| 8099619 | Voltage regulator with drive override Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock signal is powered by at least one switching-type voltage regulator. When ... | 01/17/2012 |
| 8095783 | Media boot loader A method for boot media loader that includes detecting bootable media independent of any media partitioning. When bootable media is detected, data is read from a predetermined location of the bootable media. Next, the file system type is determined from the read dat... | 01/10/2012 |
| 7840714 | Mapping SDVO functions from PCI express interface An embodiment of the present invention is a technique to map pins on an interface connector to signals for a digital display. A first group of signal traces maps transmitter differential pairs pins in a first group of lanes on the interface connector compatible with... | 11/23/2010 |
| 7506075 | Fair elevator scheduling algorithm for direct access storage device An apparatus, program product and method of processing access requests for a direct access storage device utilize a “fair elevator” algorithm to schedule access requests from a plurality of requesters desiring access to a direct access storage device (DASD). In ... | 03/17/2009 |
| 7500027 | Emulation of a disconnect of a device USB 2.0 supports communication in low-speed (LS), full speed (FS) and high speed (HS). In the full speed mode, the wire segment between a hub and a device is terminated via a pull-up resistor 480 on the D+ data line on the downstream end of the segment. In th... | 03/03/2009 |
| 7409471 | Data transfer control device for data transfer over a bus, electronic equipment and method for data transfer over a bus When a first mode (with-SOF mode) has been set, data transfer is performed while SOF packets are transferred at frame periods, and when a second mode (non-SOF mode) has been set and also non-periodic (bulk) transfer is being performed, the periodic transfer of SOF p... | 08/05/2008 |
| 7386639 | Switch for coupling one bus to another bus A communication module includes a switch circuit operable to connect an internal bus to an external bus for, e.g., diagnostics, verification, and fault analysis. The internal bus allows data communication between electronic components internal to the communication m... | 06/10/2008 |
| 7380028 | Robust delivery of video data The systems and methods described herein relate to the robust delivery of data. A transmitter (e.g. a server or RF broadcaster) passes parameters to a receiver and/or client enabling operation of a generalized buffer model within the receiver that regulates the prop... | 05/27/2008 |
| 7380032 | Storage system, and method for controlling the same Disclosed is a method A method for controlling a storage system including a host computer; a first storage controller connected communicably to the host computer, for receiving a data frame transmitted from the host computer and executing data input to and data outp... | 05/27/2008 |
| 7376757 | Driverless interfacing of a removable device with a digital product In order to avoid the need for upgrade software when enhancing the function of a digital product, e.g. PDA, and SD lookalike card or other removable device provided with an active function such as digital radio is able to create the appearance of a file structure re... | 05/20/2008 |
| 7353298 | Data transfer processing method Processing which, in conventional data transfer processing, entails the use of the common bus when performing (1) processing to confirm the interrupt state, performed via the common bus employing an interrupt register and interrupt mask register, and (2) confirmatio... | 04/01/2008 |
| 7346711 | Methods, systems, and computer program products for detecting IDE device connections Methods, systems, and computer readable mediums provide for the detection of IDE drives connected to intelligent drive electronics channels within a computer. Detection may be obtained by reading a status register destination and detecting whether data read from the... | 03/18/2008 |
| 7346714 | Notification of completion of communication with a plurality of data storage areas It is an object of this invention to expand an SBP-3 protocol such that two data buffers can be independently controlled. To achieve this object, a target sends responses to status blocks corresponding to two commands included in one ORB in the SBP-3, and an initiat... | 03/18/2008 |
| 7343430 | Methods and apparatus for improving data integrity for small computer system interface (SCSI) devices A SCSI ID of a SCSI initiator device that has won an arbitration is identified on a SCSI bus and stored in a register at a SCSI device. Subsequently, a SCSI ID of a selected SCSI target device which was selected by the SCSI initiator device is identified on the SCSI... | 03/11/2008 |
| 7340539 | Device connected to a bus for storing information utilized to allocate priority to data stored in storage device and method for operating the device A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage (i.e., memories or memory areas) in which data to be transmitted or received is temporarily stored, and a... | 03/04/2008 |
| 7340541 | Method of buffering bidirectional digital I/O lines A system and method for buffering bidirectional digital input/output (I/O) lines. The system (e.g., data acquisition system) may comprise a device including circuitry for buffering bidirectional digital lines. A first integrated circuit (IC) of the device includes a... | 03/04/2008 |
| 7340537 | Memory channel with redundant presence detect A memory agent may include a link interface having bit lanes and may utilize more than one bit lane to determine if another memory agent is also connected to the same link interface. ... | 03/04/2008 |
| 7340542 | Data processing system with bus access retraction A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of... | 03/04/2008 |
| 7337244 | Data transfer apparatus, storage device control apparatus and control method using storage device control apparatus A data transfer apparatus includes a memory having first and second queues for storing data transfer information that includes information specifying a first memory area and information specifying a second memory area, a first processor which registers the data tran... | 02/26/2008 |
| 7337248 | Adaptive synchronization method for communication in storage systems A method for transferring data in a storage system is provided. The method includes setting a catch-up threshold for accepting data requests from a port where the queue value corresponds to a number of requests collected from an input queue for every CPU interrupt, ... | 02/26/2008 |
| 7337247 | Buffer and method of diagnosing buffer failure A buffer includes an input unit that inputs data; an output unit that outputs the data; a plurality of registers that stores the data while sequentially shifting the data from the input unit to the output unit; an output-data selecting unit that selects desired data... | 02/26/2008 |
| 7333659 | Picture encoder and picture encoding method An encoder and an encoding method capable of improving the transfer efficiency in an encoding process is provided. The encoder determines the number of removed bit planes in order that the quantity of generated codes per frame is kept constant when performing the en... | 02/19/2008 |
| 7334058 | File input/output control device and method for the same background A file input/output control device for dividing a file into a plurality of fragments which are distributed to a plurality of storage devices. The file input/output control device 200, upon receiving a file from a client, constructs a plurality of fragments fr... | 02/19/2008 |
| 7334067 | Programmable controller having reduced control key set In some embodiments, a wall-mountable, programmable controller having control keys (e.g., less than eight keys or another small number of keys), a subassembly including circuitry, and a control key insert removably mountable to the subassembly and including at least... | 02/19/2008 |
| 7334068 | Physical layer device having a SERDES pass through mode A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively c... | 02/19/2008 |
| 7333328 | Hard disk system having a hard disk unit and a conversion unit for connection to a host device A large capacity HDD is handled as a portable recording medium. In a state where a portable hard disk (PHD) unit is mounted on a cradle, data is written and read between the PHD unit and a host device. By having a first engagement section on the side of the PHD unit... | 02/19/2008 |
| 7330912 | Configuration in a configurable system on a chip The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The present invention also provides certain features, transparent to the user... | 02/12/2008 |
| 7330911 | Accessing a memory using a plurality of transfers A method of operating a circuit, comprising the steps of (A) buffering a read signal received within a plurality of first transfers to the circuit, (B) transmitting the read signal in a second transfer from the circuit, (C) buffering a first write signal received in... | 02/12/2008 |
| 7330910 | Fencing of resources allocated to non-cooperative client computers Techniques are provided for processing an Input/Output (I/O) request. At least one data block is allocated for use in completing the I/O request. A current operations record is stored for the I/O request. It is determined whether the I/O request has been completed w... | 02/12/2008 |
| 7308511 | System for allocating resources in a computer system A system for allocating resources for use by devices of a computer. Device information for the devices of the computer is collected to uniquely identify the devices and to describe the device characteristics associated with the operation of those devices with the co... | 12/11/2007 |
| 7308512 | Fiber channel adaptor for serial or parallel ATA disks Coupling disks having only a single controller connection to more than one controller. An adaptor interfaces an ATA disk with two interfaces to a backplane having a fiber channel backplane interface form factor. Switching logic controls the interfaces, so the ATA di... | 12/11/2007 |
| 7296095 | Communication control method and apparatus, and communication system A printer has a queue for queuing a queued execution command, an immediate execution agent for executing a write command, and a queued execution agent for executing a read command. The immediate execution agent immediately executes the received write command, and wr... | 11/13/2007 |
| 7296094 | Circuit and method to provide configuration of serial ATA queue depth versus number of devices Disclosed is a system using a SAS host controller and SAS expanders to control multiple SATA end devices where the memory contained on the SAS host controller is fixed to ease the cost and power consumption of the SAS host controller device, but where there is an ex... | 11/13/2007 |
| 7293121 | DMA controller utilizing flexible DMA descriptors A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second me... | 11/06/2007 |
