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| Number | Title | Issue Date |
| 8190942 | Method and system for distributing a global timebase within a system-on-chip having multiple clock domains A global timebase system and method for a system-on-chip synchronizes multiple clock domains in each of a plurality of receiver modules by broadcasting a global timebase count value as Gray code over a global timebase bus. A global timebase generator includes a bina... | 05/29/2012 |
| 8180946 | Long latency interface protocol An interface configured to support a signaling protocol between a first hardware component and a second hardware component. The interface comprises a first pin, a second pin, and a third pin. The first pin is configured to provide a write clock signal sourced from t... | 05/15/2012 |
| 8176353 | Method for the data transfer between at least two clock domains The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK1) and at least one additional clock domain having a second clock rate (CLK2), comprising the following for the transfer of data from the ... | 05/08/2012 |
| 8166219 | Method and apparatus for encoding/decoding bus signal Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XO... | 04/24/2012 |
| 8161200 | Multi-protocol bus device In one general aspect, methods and devices for use with multiple communications protocols automatically determine which communications protocol to use when connected to a system bus. Signals transmitted on the system bus are monitored to determine what communication... | 04/17/2012 |
| 8156356 | Dynamic power management for internal information handling system links In some embodiments, a method for automatically and dynamically controlling the power states of physical layer links (PHYs) in a modular information handling system is provided. A chassis manager automatically determines a status of at least one of the chassis manag... | 04/10/2012 |
| 8151029 | Controlling passthrough of communication between multiple buses A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logi... | 04/03/2012 |
| 8151028 | Information processing apparatus and control method thereof An information processing apparatus connected with an IO device, having a processing unit, a channel device transferring data between the information processing apparatus and the IO device having a activation controller activating the channel device, a storage devic... | 04/03/2012 |
| 8127154 | Total cost based checkpoint selection A cost associated with taking a checkpoint is determined. The cost includes an energy cost. An interval between checkpoints is computed so as to minimize the cost. An instruction is sent to schedule the checkpoints at the computed interval. The energy cost may furth... | 02/28/2012 |
| 8127067 | High latency interface between hardware components A hard disk controller including a first circuit, a second circuit, a third circuit, and a mode circuit. The first circuit is configured to transmit a first signal to control data transfer between the hard disk controller and a read/write channel circuit. The second... | 02/28/2012 |
| 8117369 | Input-output module for operation in memory module socket and method for extending a memory interface for input-output operations An I/O module configured to operate in a memory module socket and method for extending a memory interface are generally described herein. The I/O module may include a serial-presence detection (SPD) device to indicate that the I/O module is an I/O device and to indi... | 02/14/2012 |
| 8117367 | Processor system with an application and a maintenance function A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors ha... | 02/14/2012 |
| 8112572 | Apparatus for swapping high-speed multimedia signals An apparatus for swapping output high-speed multimedia signals. In one embodiment the apparatus comprises a plurality of inputs coupled to a multimedia transmitter; a plurality of outputs coupled to a plurality of pins of a multimedia interface connector; and a cont... | 02/07/2012 |
| 8108581 | Information processing apparatus According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first transmission speed or a second transmission speed lower than the first tran... | 01/31/2012 |
| 8103817 | Systems for accessing memory card and methods for accessing memory card by a control unit A system for accessing a memory card is provided. The system includes a control unit having a control pin and a processor. The processor senses a card-insertion signal from a socket via the control pin for indicating whether the memory card has been inserted into th... | 01/24/2012 |
| 8099540 | Reconfigurable circuit A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first con... | 01/17/2012 |
| 8078783 | Information processing apparatus, method for controlling the same, and recording medium including program An information processing apparatus includes a card slot to which a card-type medium is inserted, a determination unit configured to determine an operation mode, from among a first, second and third operation modes, which attains the highest speed of data communicat... | 12/13/2011 |
| 8073984 | Communication protocol for use with portable electronic devices Improved techniques for communicating between a portable electronic device and an accessory (or auxiliary) device are disclosed. The accessory device can augment or supplement the functionality or capabilities of the portable electronic device. For example, in one e... | 12/06/2011 |
| 8069290 | Processing system operable in various execution environments A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at... | 11/29/2011 |
| 8060664 | Integrated circuit having a plurality of interfaces and integrated circuit card having the same An integrated circuit supporting a first interface and a second interface and an integrated circuit card having the same includes the first interface capable of communicating with a first host, the second interface communicating with a second host, and a control blo... | 11/15/2011 |
| 8060679 | Information processing apparatus and access control method capable of high-speed data access Requestors acquire tokens before issuing access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a... | 11/15/2011 |
| 8060768 | Power saving method of portable internet device and portable internet device thereof, and instant messaging system using the same The present invention discloses a power saving method of a portable Internet device, the portable Internet device and its instant messaging system. If a screen of the portable Internet device is in non-view state, for example, both backlight module and LCD panel are... | 11/15/2011 |
| 8060770 | Method and system for clock skew reduction in clock trees A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of f... | 11/15/2011 |
| 8060677 | Real-time industrial ethernet ethercat communication control A real-time industrial Ethernet EtherCAT system including a communication master and a plurality of slave nodes, wherein one slave node acts as a logic control master and the further slave nodes act as logic control slaves, and wherein a communication flow is as fol... | 11/15/2011 |
| 8060682 | Method and system for multi-level switch configuration System and method to configure switch systems are disclosed. A switch system includes leaf modules with internal ports and spine modules with ports. A midplane includes first layers closer to a first side, second layers closer to a second side and third layers betwe... | 11/15/2011 |
| 8055809 | System and method for distributing signal with efficiency over microprocessor A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an eve... | 11/08/2011 |
| 8055828 | Electronic power management system An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for in... | 11/08/2011 |
| 8041970 | Cluster system with reduced power consumption and power management method thereof Provided are a cluster system, which can reduce power consumption by controlling power at a cluster level according to loads, and a power management method of the cluster system. The cluster system includes a plurality of management target nodes for performing an ac... | 10/18/2011 |
| 8037327 | System and method for improving dynamic response in a power supply A system for improving dynamic response in a power supply includes a mainframe module having a memory and a mainframe microprocessor, the mainframe processor configured to calculate a plurality of tables in which each table represents a current/voltage (I/V) charact... | 10/11/2011 |
| 8028116 | Data transfer apparatus and data transfer method A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data transferred between a CPU 133, an I/O devic... | 09/27/2011 |
| 8028107 | Apparatus and method for serial to parallel in an I/O circuit A serial to parallel I/O circuit apparatus includes M sequential logic circuits and each of them includes a first D-type flip-flop for receiving one bit of input data, and the output of each the first D-type flip-flop connects to the input of a first D-type flip-flo... | 09/27/2011 |
| 8024504 | Processor interrupt determination Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targe... | 09/20/2011 |
| 8024590 | Predicting future power level states for processor cores In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor package to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the ... | 09/20/2011 |
| 8015324 | Method for data transmission The invention relates to a method for data transmission in a serial bus system comprising a control unit and bus users. The method comprises steps: receiving a first data telegram by a bus user from the control unit, wherein the data telegram has a data field contai... | 09/06/2011 |
| 8015336 | Method of compensating for propagation delay of tri-state bidirectional bus in a semiconductor device A semiconductor device for detecting and compensating for a propagation delay of a tri-state bidirectional bus connected between a master block and a plurality of slave blocks. The master block controls the slave blocks. A bidirectional bus connects the master block... | 09/06/2011 |
| 8010714 | Method for assigning addresses to nodes of a bus system, and installation A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery... | 08/30/2011 |
| 8010730 | Bus converter, semiconductor device, and noise reduction method of bus converter and semiconductor device A bus converter is disclosed that converts a signal of a synchronous bus into a signal of an asynchronous bus. The bus converter includes a control signal generation unit that generates n control signals synchronized at different timings of a predetermined synchroni... | 08/30/2011 |
| 8001287 | Dynamically updating alias location codes with correct location codes during concurrent installation of a component in a computer system During an initial generation/assignment of location codes for field replaceable units (FRUs) that are and/or may be attached to the computer system, the service processor provides an alias location code for each FRU not currently attached. When the service processor... | 08/16/2011 |
| 7996593 | Interrupt handling using simultaneous multi-threading Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information processing system in a simultaneous multi-threading mode. At least a first logi... | 08/09/2011 |
| 7984206 | System for debugging throughput deficiency in an architecture using on-chip throughput computations A method, system, and apparatus for debugging throughput deficiency in an architecture using on-chip throughput computations are disclosed. In one embodiment, a system includes a subsystem module of the integrated circuit (e.g., may be a field-programmable gate arra... | 07/19/2011 |
