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| Number | Title | Issue Date |
| 6185703 | Method and apparatus for direct access test of embedded memory An apparatus includes an embedded memory, a plurality of input connectors to receive input signals from an external source, a plurality of output connectors to provide output signals to the external source, and a plurality of reconfigurable input and outp... | 02/06/2001 |
| 6185661 | Worm magnetic storage device A method for operating a magnetic disk storage device in read/write and read-only modes. A control program in a system cache memory receives write requests for transferring data to a logical volume. The control program determines whether the write request... | 02/06/2001 |
| 6181638 | Method for receiving data from a synchronous random access memory One embodiment of the present invention provides a method for receiving data from a synchronous random access memory. This method receives a stream of data along with a data clock signal from the synchronous random access memory. This stream of data is al... | 01/30/2001 |
| 6178517 | High bandwidth DRAM with low operating power modes A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used ... | 01/23/2001 |
| 6173357 | External apparatus for combining partially defected synchronous dynamic random access memories The present invention discloses an apparatus for combining partially defected synchronous dynamic random access memories. By selecting each memory chip with corresponding workable blocks, the partially defected SDRAMs can be combined as a workable device ... | 01/09/2001 |
| 6173365 | Cache memory system and method of a computer A high-performance and cost-effective cache memory system is provided for use in conjunction with a high-speed computer system. The cache memory system is used on a computer system having a central processing unit (CPU) of the type having a back-off funct... | 01/09/2001 |
| 6157559 | Apparatus and method for updating ROM without removing it from circuit board An updater device for flash read-only memory is provided. The updater device may be constructed using a power input interface that transfers battery from either a battery or an electrical adapter to the updater device. The updater device has a body contai... | 12/05/2000 |
| 6157993 | Prefetching data using profile of cache misses from earlier code executions During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the pro... | 12/05/2000 |
| 6148375 | Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes A method of maintaining cache coherency in a shared memory multiprocessor system having a plurality of nodes, where each node itself is a shared memory multiprocessor. With this invention, an additional shared owner state is maintained so that if a cache ... | 11/14/2000 |
| 6145065 | Memory access buffer and reordering apparatus using priorities A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memo... | 11/07/2000 |
| 6141739 | Memory Interface supporting access to memories using different data lengths A computing device (10) includes a processor (14) coupled to a memory interface (28). The memory interface (28) supports access to a variety of memories (12) using at least two different data lengths. The memory interface (28) includes an address register... | 10/31/2000 |
| 6138215 | Method for absolute address history table synonym resolution A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base... | 10/24/2000 |
| 6134640 | Method for transforming flash memory storage format based on average data length A method for transforming a logic format includes dividing a data segment into a main data segment having a main segment length and a sub data segment having a sub segment length shorter than the main segment length, allotting the main data segment and th... | 10/17/2000 |
| 6128693 | Bank pointer comparator and address generator for a DVD-ROM system An data processing apparatus for a digital versatile disk ROM system includes an EFM demodulator, an error-correction decoder, and a data transfer unit, each of which is interfaced with an external memory partitioned into first, second, and third banks fo... | 10/03/2000 |
| 6115802 | Efficient hash table for use in multi-threaded environments A lockless-lookup hash table for use in a multi-threaded processing system has a memory whose storage locations hold elements. Each memory location is uniquely identified by an index value, and each element includes a key and a value. The target location ... | 09/05/2000 |
| 6115793 | Mapping logical cache indexes to physical cache indexes to reduce thrashing and increase cache size A cache memory system which minimizes the latency and latency uncertainty of data memory access by allocating spare cache memories to subsequent conflicting requests, and maintaining the prior requests in a separate table until the prior request is satisf... | 09/05/2000 |
| 6112286 | Reverse mapping page frame data structures to page table entries A system, method and computer program product for reverse mapping a page of memory to one or more data structure references, such as page table entries, that reference the page of memory. A number m of fields of a page frame data structure are reserved fo... | 08/29/2000 |
| 6112281 | I/O forwarding in a cache coherent shared disk computer system A method and apparatus for I/O forwarding in a cache coherent shared disk computer system is provided. According to the method, a requesting node transmits a request for requested data to a managing node. The managing node receives the read request from t... | 08/29/2000 |
| 6105104 | Method and apparatus for optimizing the data transfer rate to and from a plurality of disk surfaces A method of mapping sequential logical data blocks to multiple disk surfaces. Data blocks are written to a predetermined number of adjacent tracks on each surface before performing a head switch to write data on another surface. The predetermined number o... | 08/15/2000 |
| 6101581 | Separate victim buffer read and release control In accordance with the present invention, a method and apparatus is provided for maintaining the coherency of victim data from a time when the data is stored in a victim data buffer until a time when the data is written into a main memory. Alternatively, ... | 08/08/2000 |
| 6088780 | Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an a... | 07/11/2000 |
| 6081871 | Cache system configurable for serial or parallel access depending on hit rate A data processing system having a CPU (central processing unit), a system bus and a main memory connected to the system bus, comprises a cache memory connected to the system bus for storing a predetermined part of data stored at the main memory, a first p... | 06/27/2000 |
| 6078985 | Memory system having flexible addressing and method using tag and data bus communication A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the contr... | 06/20/2000 |
| 6079004 | Method of indexing a TLB using a routing code in a virtual address The method serves to operate an address translation device for translating a virtual address of a virtual address space comprising a plurality of pages into a physical address of a physical address space comprising a plurality of pages, with the use of a ... | 06/20/2000 |
| 6061773 | Virtual memory system with page table space separating a private space and a shared space in a virtual memory A virtual memory system includes a virtual address space including a process private space, a shared space, and a page table space located between the process private space and the shared space. The page table space includes page table entries mapping bot... | 05/09/2000 |
| 6058452 | Memory cells configurable as CAM or RAM in programmable logic devices A programmable logic device having content addressable memory is disclosed. In a preferred embodiment, the programmable logic device includes reconfigurable dual mode memory suitable for operating as a content addressable memory in a first mode and a rand... | 05/02/2000 |
| 6047363 | Prefetching data using profile of cache misses from earlier code executions During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the pro... | 04/04/2000 |
| 6044433 | DRAM cache A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fab... | 03/28/2000 |
| 6041395 | System and method for changing partition mappings to logical drives in a computer memory A system and method for changing partition mappings to logical drives in a memory device of a computer. The computer includes a processor for running operating system code and a hard drive. The hard drive, which can be accessed by the processor, includes ... | 03/21/2000 |
| 6041386 | Data sharing between system using different data storage formats Disclosed is a system, typically implemented in a storage controller, for extracting data from a device storing data in a first format, such as the count-key-data (CKD) format. The first format is comprised of a plurality of tracks. Each track has at leas... | 03/21/2000 |
| 6032239 | System and method for updating partition mappings to logical drives in a computer memory device A system and method for changing partition mappings to logical drives in a memory device of a computer. The computer includes a processor for running operating system code and a hard drive. The hard drive, which can be accessed by the processor, includes ... | 02/29/2000 |
| 6029237 | Method for simulating the presence of a diskette drive in a NetPC computer that contains only a hard disk drive A system and method for re-mapping a logical reference to a computer storage device to another storage device. The computer includes a processor for running operating system code, RAM, and a hard drive memory device. The computer does not, however, have a... | 02/22/2000 |
| 6016537 | Method and apparatus for address multiplexing to support variable DRAM sizes Each of a plurality of output circuits is coupled with one pair of a plurality of pairs of adjacent odd and even bits of a sequential group of address bits. The output circuits provide an address bus with the odd address bits during a first time period an... | 01/18/2000 |
| 6014724 | Flash translation layer block indication map revision system and method A system and method of avoiding preservation of files deleted in a flash memory by indicating deletion in a File Indication Map without modifying an associated block allocation map controls transfer of files from a full flash memory erase unit to a transf... | 01/11/2000 |
| 6009494 | Synchronous SRAMs having multiple chip select inputs and a standby chip enable input A synchronous SRAM module comprises first and second SRAM chips. Each SRAM chip has three chip enable inputs. A module enable and memory selection circuit is coupled to the two SRAM chips to perform the dual tasks of (1) selectively enabling or disabling ... | 12/28/1999 |
| 6003123 | Memory system with global address translation A multiprocessor system having shared memory uses guarded pointers to identify protected segments of memory and permitted access to a location specified by the guarded pointer. Modification of pointers is restricted by the hardware system to limit access ... | 12/14/1999 |
| 6003117 | Secure memory management unit which utilizes a system processor to perform page swapping An integrated circuit accesses encrypted data stored in an external memory, the integrated circuit includes a main memory for storing decrypted data. A processor within the integrated circuit utilizes the decrypted data in the main memory. A soft secure m... | 12/14/1999 |
| 5987581 | Configurable address line inverter for remapping memory A flexible memory mapper for selectively inverting the state of an address line on an address bus includes a selectable inverter element and a control circuit. The selectable inverter element has a control input coupled to an output of the control circuit... | 11/16/1999 |
| 5970512 | Translation shadow array adder-decoder circuit for selecting consecutive TLB entries A combined adder/decoder calculates a field within an effective address necessary to access a translation array. Rather than adding the full lengths of the previous fetch address and offset, only the bits corresponding to the field are added. A carry-in v... | 10/19/1999 |
| 5956756 | Virtual address to physical address translation of pages with unknown and variable sizes A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page ... | 09/21/1999 |
