Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 5156984 | Manufacturing method for a Bi-CMOS by trenching A manufacturing method for a Bi-CMOS by trenching which is allowed to manufacture the bipolar celement and CMOS element simultaneously on one substrate by trench etching, comprising the processes of growing an oxide layer, forming N+ buried la... | 10/20/1992 |
| 5086011 | Process for producing thin single crystal silicon islands on insulator A semiconductor fabrication process uses an epitaxial layer as an etch stop in a plasma etch process. In one embodiment, mechanical stops and an epitaxial layer are used in combination for stopping precisely at a desired end point.... | 02/04/1992 |
| 5084399 | Semi conductor device and process for fabrication of same In a contact type image sensor prepared by disposing a plurality of sandwich type photoelectric conversion elements each of which is obtained by sandwiching an amorphous semiconductor layer as a photoelectric conversion layer between a metal electrode and... | 01/28/1992 |
| 4996166 | Process for fabricating a heterojunction bipolar transistor A heterojunction bipolar transistor includes a base layer and a wide bandgap emitter layer. A portion of the base layer is exposed, a base electrode is formed thereon and the active region of the emitter-base junction is limited inside a semiconductor bod... | 02/26/1991 |
| 4994407 | Radiation hardened field oxides for NMOS and CMOS-bulk and process for forming The field oxide surrounding an NMOS device or the field oxide around the NMOS device and between the NMOS and PMOS devices in CMOS is split or notched to make at least one thin field oxide region under which a degenerative P+ region is formed in the subst... | 02/19/1991 |
| 4975390 | Method of fabricating a semiconductor pressure sensor Herein disclosed is a semiconductor pressure sensor and a method of manufacture. The sensor includes a plate having a recess in its main surface. A diaphragm has a lower surface therof bonded to a first main surface of the plate and formed so as to have a... | 12/04/1990 |
| 4968643 | Method for fabricating an activatable conducting link for metallic conductive wiring in a semiconductor device A conducting link is disposed in an insulating layer of a semiconductor device in combination with a plurality of wirings of the device which are electrically separated from each other. The conducting link is selectively activated to provide the wirings w... | 11/06/1990 |
| 4965219 | Method for the manufacturing of insulated gate field effect transistors (IGFETS) having a high response speed in high density integrated circuits The method involves the formation above the substrate of regions of epitaxial type automatically aligned with the gate electrode and designed to form the source and drain regions of the transistor. These regions are doped by ion implantation using a compa... | 10/23/1990 |
| 4962053 | Bipolar transistor fabrication utilizing CMOS techniques Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is op... | 10/09/1990 |
| 4962052 | Method for producing semiconductor integrated circuit device A method for producing a memory LSI having in its peripheral circuitry an MISFET of LDD structure and a vertical type bipolar transistor is disclosed. More particularly, an impurity for forming a low impurity concentration region of the said MISFET of LDD... | 10/09/1990 |
| 4960729 | Integrated circuits and a method for manufacture thereof A technique for providing a radiation formable conductive link in an integrated circuit comprising the steps of: depositing a plurality of aluminum conductors on an exposed surface of an otherwise completed integrated circuit, and forming a bridge of amor... | 10/02/1990 |
| 4954457 | Method of making heterojunction bipolar transistors Heterojunction bipolar transistor technology employing in a body wherein a larger area base electrode over a buried electrode has above it a smaller area electrode, an overhang capability on the portion of the smaller area electrode that operates to mask ... | 09/04/1990 |
| 4954455 | Semiconductor memory device having protection against alpha strike induced errors The invention comprises an improved bipolar memory device having enhanced protection against the effects of alpha particles comprising at least one memory cell having a buried layer forming at least a portion of the collector of one of the transistors in ... | 09/04/1990 |
| 4954456 | Fabrication method for high speed and high packing density semiconductor device (BiCMOS) A fabrication method for a high speed and high packing density semiconductor device (BiCMOS) in which high speed polysilicon self-aligned bipolar transistors and high packing density CMOS are contained on the same wafer in such a manner that simplicity in... | 09/04/1990 |
| 4948752 | Method of making sagfets on buffer layers A composite buffer layer is formed with a layer of GaAs on a semi-insulating GaAs substrate. Next a short period superlattice is formed followed by another GaAs layer, whereon is formed a first AlGaAs layer having a first mole fraction of Al and a second ... | 08/14/1990 |
| 4948757 | Method for fabricating three-dimensional microstructures and a high-sensitivity integrated vibration sensor using such microstructures A method for preferentially etching phosphosilicate glass to form a micromechanical structure includes forming a layer of phosphosilicate glass on a substrate and opening at least one via in the phosphosilicate glass layer. A layer of material which is pa... | 08/14/1990 |
| 4946798 | Semiconductor integrated circuit fabrication method In a semiconductor integrated circuit fabrication method, isolated regions are in a silicon substrate, which is then covered with polysilicon, a passive base region is then formed, the polysilicon is selectively oxidized, the unoxidized polysilicon is the... | 08/07/1990 |
| 4944682 | Method of forming borderless contacts A method of forming semi-conductor devices components wherein there are at least two exposed conducting regions having passivating material overlying said regions. The passivating material is subject to etching by a given etchant. At least one, but less t... | 07/31/1990 |
| 4940671 | High voltage complementary NPN/PNP process A process is disclosed for forming high-performance high-voltage PNP transistors in a conventional monolithic, planar, PN junction isolated integrated circuit that contains high-performance NPN transistors. The process permits independently optimizing the... | 07/10/1990 |
| 4933300 | Process for forming multilayer thin film A superlattice film is formed by introducing a mixture of a first gas reactant capable of only plasma-excited chemical reaction and a second gas reactant capable of both plasma-excited chemical reactions into a reaction chamber, discontinuously carrying o... | 06/12/1990 |
| 4933295 | Method of forming a bipolar transistor having closely spaced device regions A method of forming a bipolar transistor comprising the steps of forming a base region in a semiconductor structure and disposing an emitter region on a surface of a first portion of the base region, the emitter region having upper and side surfaces. An a... | 06/12/1990 |
| 4929570 | Selective epitaxy BiCMOS process A process for fabricating both bipolar and complementary field effect transistors in an integrated circuit is disclosed. The process begins with a structure having a P type substrate 10, an N type epitaxial layer 15, and an intervening N type buried layer... | 05/29/1990 |
| 4927471 | Semiconductor substrate comprising wafer substrate and compound semiconductor layer A semiconductor substrate including a top epitaxial compound layer comprising: a single-crystalline semiconductor wafer substrate; a strained layer superlattice (SLS) structure layer having a lattice constant varying from that of the wafer substrate to th... | 05/22/1990 |
| 4927785 | Method of manufacturing semiconductor devices A method of manufacturing semiconductor devices is set forth using reactive ion plasma etching in which an optical grating is formed to etch underlying regions, such as dielectric material, semiconductor material, or alternate layers of different semicond... | 05/22/1990 |
| 4927784 | Simultaneous formation of via hole and tube structures for GaAs monolithic microwave integrated circuits A method of simultaneously forming recesses for via holes and tube structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a pl... | 05/22/1990 |
| 4921811 | Semiconductor integrated circuit device and a method for manufacturing the same An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface ... | 05/01/1990 |
| 4920075 | Method for manufacturing a semiconductor device having a lens section A method for manufacturing a semiconductor device with a lens section. A semiconductor element is formed in a semiconductor substrate and a transparent layer is formed on this semiconductor element. The transparent layer is patterned to form the lens sect... | 04/24/1990 |
| 4918032 | Method for fabricating three-dimensional microstructures and a high-sensitivity integrated vibration sensor using such microstructures A method for preferentially etching phosphosilicate glass to form a micromechanical structure includes forming a layer of phosphosilicate glass on a substrate and opening at least one via in the phosphosilicate glass layer. A layer of material which is pa... | 04/17/1990 |
| 4918026 | Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip A process is used to form in a common substrate a PMOS transistor of the lightly doped drain (LDD) type, an NMOS transistor of the LDD type and a vertical n-p-n bipolar transistor. In particular: the steps used to form an n-type well for the PMOS transist... | 04/17/1990 |
| 4918030 | Method of forming light-trapping surface for photovoltaic cell and resulting structure An improved textured surface of a photovoltaic device is provided by an anisotropic etching process in which pyramidal structures are formed on a silicon surface having a (100) crystallographic orientation. An aqueous solution of an alkali metal hydroxide... | 04/17/1990 |
| 4916083 | High performance sidewall emitter transistor A novel vertical bipolar device endowed with a lithography-independent tightly controlled submicron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic ba... | 04/10/1990 |
| 4914048 | Method of making Bicmos devices A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for t... | 04/03/1990 |
| 4914055 | Semiconductor antifuse structure and method A method for forming an array of antifuse structures on a semiconductor substrate which previously has had CMOS devices fabricated thereupon up to first metallization. A fuse structure is formed as a sandwich by successively depositing a bottom layer of T... | 04/03/1990 |
| 4912066 | Make-link programming of semiconductor devices using laser-enhanced thermal breakdown of insulator A semiconductor device is programmed by a laser beam which causes an insulator between two conductors on a silicon substrate to be permanently altered, as by breakdown of the insulator. The conductors may be metals such as aluminum or tungsten, and the in... | 03/27/1990 |
| 4910170 | Method of manufacturing semiconductor device In the invention, the width of the emitter contact layer is determined in accordance with the width of a first side wall, and the junction distance between a base contact layer and the emitter contact layer is determined in accordance with the width of a ... | 03/20/1990 |
| 4907974 | Method of growing a semiconductor device structure A semiconductor device includes a plurality of crystalline layers successively disposed directly on a substrate or on a buffer layer on the substrate and a getter layer comprising a metal of high activity disposed between the substrate or the buffer layer... | 03/13/1990 |
| 4904612 | Method for manufacturing a planar, self-aligned emitter-base complex A method for the manufacture of a planar, self-aligned emitter-base complex, whereby a semiconductor layer structure standard for hetero-bipolar transistors is first grown on a substrate, the base regions are subsequently etching through a mask technique ... | 02/27/1990 |
| 4902633 | Process for making a bipolar integrated circuit A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy on top of a substrate. The first epitaxial layer is of the same conductivity type as the substrate and adds additional height to the substrate surroun... | 02/20/1990 |
| 4892837 | Method for manufacturing semiconductor integrated circuit device Disclosed is a method of producing a bipolar transistor which enables an external base region, an intrinsic base region and an emitter region to be formed in self-alignment with respect to the base electrode. More specifically, the method comprises the st... | 01/09/1990 |
| 4892840 | EPROM with increased floating gate/control gate coupling Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between t... | 01/09/1990 |
