Bizarre Patents
Reward Candy Dispenser for Personal Computers
A personal computer peripheral, battery powered reward candy dispenser which immediately presents students with a single candy for each problem completed correctly.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7541277 | Stress relaxation, selective nitride phase removal A method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of BEOL conductors, and chemical-mechanica... | 06/02/2009 |
| 7462868 | Light emitting diode chip with double close-loop electrode design An LED chip with double close-loop electrode design includes a substrate, a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer, a first electrode and a second electrode. The first-type doped semiconductor layer is d... | 12/09/2008 |
| 7459787 | Multi-layered copper line structure of semiconductor device and method for forming the same A multi-layered copper line structure of a semiconductor device with a lower copper line, an upper copper line, and a via contact, which electrically connects the lower copper line and the upper copper line, can incorporate one or more dummy via contacts to reduce t... | 12/02/2008 |
| 7459790 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 12/02/2008 |
| 7459791 | Post passivation interconnection schemes on top of IC chip A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 12/02/2008 |
| 7459335 | Solid-state imaging apparatus and method for producing the same A solid-state imaging apparatus includes a plurality of photosensitive cells, and a driving unit provided for driving the plurality of photosensitive cells. Each photosensitive cell includes a photodiode formed to be exposed on a surface of a semiconductor substrate... | 12/02/2008 |
| 7453100 | DFB laser assembly and laser module A DFB laser assembly including both a DFB laser device, with a buried heterostructure having a cavity length of 400 μm, a differential resistance of 4Ω, an emission wavelength of 1550 nm, and a thermal resistance of 50K/watt or less, and a heat sink mounting the D... | 11/18/2008 |
| 7449416 | Apparatus and plasma ashing process for increasing photoresist removal rate A plasma ashing process for removing photoresist material and post etch residues from a substrate comprising carbon, hydrogen, or a combination of carbon and hydrogen, wherein the substrate comprises a low k dielectric layer, the process comprising forming a plasma ... | 11/11/2008 |
| 7446040 | Structure for optimizing fill in semiconductor features deposited by electroplating A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metalliz... | 11/04/2008 |
| 7442565 | Method for manufacturing vertical structure light emitting diode A method for manufacturing a vertical light emitting diode of the invention allows an easier process of individually separating chips. A light emitting structure is formed on a growth substrate having a plurality of device areas and at least one device isolation are... | 10/28/2008 |
| 7442634 | Method for constructing contact formations According to one aspect of the invention, a method for forming contact formations is provided. A substrate may be placed in an electrolytic solution. The substrate may have an exposed conductive portion and the electrolytic solution may include a plurality of metall... | 10/28/2008 |
| 7442578 | Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of underfilling micoelectronic devices Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of disposing underfill including electrically charged filler elements on microelectroni... | 10/28/2008 |
| 7440253 | Protective device A protective device for transmitting electromagnetic signals of a desired frequency band from a source to a load comprises an outer conductor, an inner conductor extending coaxially within the outer conductor and a quarter wavelength shunt conductor. A radio frequen... | 10/21/2008 |
| 7439096 | Semiconductor device encapsulation An encapsulated semiconductor device and method wherein an encapsulant material is deposited on the device in an environment that enhances device performance. Illustrative encapsulant materials are organic polymers, silicon polymers and metal/polymer-layered encapsu... | 10/21/2008 |
| 7439615 | Semiconductor component comprising an integrated semiconductor chip and a chip housing, and electronic device A semiconductor component includes an integrated semiconductor chip and a chip housing. The chip housing has first, second, third and fourth conductor tracks that connect input and output connections of the semiconductor chip to external contact connections on the u... | 10/21/2008 |
| 7439182 | Semiconductor device and method of fabricating the same A semiconductor and a method of fabricating the same are provided. The method includes: forming an insulation layer on a substrate; forming a trench by selectively etching the insulation layer; electroplating a copper layer in the trench and on the insulation layer ... | 10/21/2008 |
| 7435606 | Light emitting devices and method for fabricating the same Light emitting devices and a method for fabricating the same have an advantage in that an etching film formed between a plurality of light emitting structures is removed to separate respective lateral surfaces of the light emitting structures from one another, and a... | 10/14/2008 |
| 7435671 | Trilayer resist scheme for gate etching applications A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme... | 10/14/2008 |
| 7432218 | Method for producing porous body A process of a porous body comprises the steps of disposing a first material in which pores are formed by anodization on a substrate to form a first layer, disposing on the first layer a second material which has a hardness lower than that of the first material and ... | 10/07/2008 |
| 7429540 | Silicon oxynitride gate dielectric formation using multiple annealing steps A method for processing a semiconductor substrate in a chamber includes forming a silicon oxynitride film using a two-step anneal process. The first anneal step includes annealing the silicon oxynitride film in the presence of an oxidizing gas that has a partial pre... | 09/30/2008 |
| 7427528 | CMOS image sensor and method for fabricating the same A CMOS image sensor and a method for fabricating the same in which color balance is enhanced by forming photodiodes to have a depth varied according to the wavelength of incident light to be received through a color filter layer. The predetermined depth varies, from... | 09/23/2008 |
| 7425507 | Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross s... | 09/16/2008 |
| 7425471 | Semiconductor structure processing using multiple laser beam spots spaced on-axis with cross-axis offset Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first laser beam that propagates ... | 09/16/2008 |
| 7423343 | Wiring board, manufacturing method thereof, semiconductor device and manufacturing method thereof The invention provides a wiring board having a small-scale and high-performance functional circuit while realizing a multi-layer wiring with a small number of steps. In addition, the invention provides a semiconductor device in which a display device is integrated w... | 09/09/2008 |
| 7419900 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 09/02/2008 |
| 7419854 | Methods for packaging image sensitive electronic devices The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS chips. In one embodiment of the invention, an image sensor package is assembled by surrounding a chip with a ... | 09/02/2008 |
| 7416997 | Method of fabricating semiconductor device including removing impurities from silicon nitride layer A method of fabricating a semiconductor device having a silicon nitride layer substantially free of impurities includes forming a silicon nitride layer on a semiconductor substrate and annealing the semiconductor substrate having the silicon nitride layer in an atmo... | 08/26/2008 |
| 7417317 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 08/26/2008 |
| 7417323 | Neo-wafer device and method A neo-wafer made from integrated circuit die and methods for making a neo-wafer are disclosed. A substrate is provided and includes a dielectric layer with conductive pads for the receiving of one or more integrated circuit die. Die are flip-chip bonded to the condu... | 08/26/2008 |
| 7417254 | Switching device for a pixel electrode and methods for fabricating the same The invention discloses a switching devise for a pixel electrode of display devise and methods for fabricating the same. A gate is formed on a portion of a substrate. A semiconductor layer is formed on the gate. A source and a drain are formed on a portion of the se... | 08/26/2008 |
| 7414282 | Method of manufacturing a non-volatile memory device A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to... | 08/19/2008 |
| 7413956 | Semiconductor device manufacturing method Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, in which active and inactive regions are separated by a field oxidation film; source/drain junctions contacting the field oxida... | 08/19/2008 |
| 7410889 | Method of fabricating a poly-silicon thin film A silicon layer and a heat-retaining layer are formed on a substrate in turn, and a laser beam with a sharp energy density gradient is next utilized to perform a laser heating process for inducing super lateral growth crystallization occurred in part of the Si layer... | 08/12/2008 |
| 7410816 | Method for forming a chamber in an electronic device and device formed thereby A method is disclosed for forming a chamber in an electronic device, including the steps of preparing an outer surface on a solidified core material, the solidified core material in a depression formed in a substrate. The method further includes establishing a layer... | 08/12/2008 |
| 7411280 | Chip support of a leadframe for an integrated circuit package The central region of a leadframe (101, 201, 301, 401, 501, 601, 701, 801, 901, 1001, 1101, 1201), is selectively etched to leave upright portions (104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204). Subsequently, during the packaging proce... | 08/12/2008 |
| 7408222 | Charge trapping device and method of producing the charge trapping device A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semicond... | 08/05/2008 |
| 7407883 | Electronic package with improved current carrying capability and method of forming the same An electronic package and method for forming such package that expands the current capability of lines and/or reducing line resistance for packages with a given feature dimension while relaxing feature tolerances. The methods and structures include electrical wiring... | 08/05/2008 |
| 7402503 | Dicing sheet, manufacturing method thereof, and manufacturing method of semiconductor apparatus A dicing sheet which supports electronic-component aggregation with adhesive in the case of separating the electronic-component aggregation in which a plurality of electronic components are integrated, has a substrate and an adhesion layer which is formed at one sur... | 07/22/2008 |
| 7402491 | Methods of manufacturing a semiconductor device including a dielectric layer including zirconium A method of manufacturing a semiconductor device can include forming a tunnel oxide layer on a substrate, forming a floating gate on the tunnel oxide layer and forming a dielectric layer pattern on the floating gate using an ALD process. The dielectric layer pattern... | 07/22/2008 |
| 7402871 | Semiconductor device having resistor and method of fabricating the same In a semiconductor device having a resistor and a method of fabricating the same, the device includes a semiconductor substrate having a cell region and a peripheral region. A lower interlayer insulating layer is disposed on the semiconductor substrate. A buffer pad... | 07/22/2008 |
