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| Number | Title | Issue Date |
| 7752518 | System and method for increasing the extent of built-in self-testing of memory and circuitry An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the externa... | 07/06/2010 |
| 7464226 | Fractional caching A microprocessor-based system generates an electronic document based on a set of microprocessor-readable instructions organized in logical units known as instruction nodes. Each instruction node includes at least one microprocessor-readable instruction. If an instru... | 12/09/2008 |
| 7464237 | System and method for implementing a fast file synchronization in a data processing system A system and method for implementing a fast file synchronization in a data processing system. A memory management unit divides a file stored in system memory into a collection of data block groups. In response to a master (e.g., processing unit, peripheral, etc.) mo... | 12/09/2008 |
| 7461203 | Disk array apparatus and method for controlling the same An apparatus includes a controller and a plurality of disk drives. The controller has a communication control unit for accepting a data input/output request, a disk controller unit for controlling a disk drive, and a cache memory for temporarily storing data transfe... | 12/02/2008 |
| 7461214 | Method and system for accessing a single port memory In a method of accessing a single port memory, a plurality of read commands are received from a plurality of requestors for memory read access. A respective plurality of parameters corresponding to each of the plurality of read commands is stored in a memory read co... | 12/02/2008 |
| 7461198 | System and method for configuration and management of flash memory A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is confi... | 12/02/2008 |
| 7461212 | Non-inclusive cache system with simple control operation A cache system includes a processing device operative to access a main memory device, a primary cache coupled to the processing device and accessible from the processing device at faster speed than the main memory device, and a secondary cache coupled to the process... | 12/02/2008 |
| 7461216 | Memory controller A memory controller for accessing a memory module comprising a plurality of memory banks. The memory controller is operable to write copies of program data to one or more memory banks according to the size of the program data. The memory controller is additionally o... | 12/02/2008 |
| 7461219 | Disk drive and method for performing realtime processing and non-realtime processing simultaneously Embodiments of the invention ensure both a realtime nature of a realtime processing and data integrity of a non-realtime processing and perform the both processings efficiently when the realtime processing and the non-realtime processing are performed simultaneously... | 12/02/2008 |
| 7461211 | System, apparatus and method for generating nonsequential predictions to access a memory A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher inclu... | 12/02/2008 |
| 7461208 | Circuitry and method for accessing an associative cache with parallel determination of data and data availability A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine wh... | 12/02/2008 |
| 7457907 | Method and circuit for interfacing card memory, asic embedded with the interface circuit, and image forming apparatus equipped with the asic An SD card interface, which is an interface for a detachable SD card requiring an access in sector units (a specific size), has a function to initialize an SD controller, a function to initialize an SD card, and a function to acquire status of the SD card. ... | 11/25/2008 |
| 7457919 | Method for memory page management A method for memory page management, suitable for managing data stored in several memory blocks is disclosed, which includes the following steps. First, multiple pages is recorded in a first register. When a request for reading data is received, whether the data is ... | 11/25/2008 |
| 7457914 | Asynchronous event notification Described is a technique for asynchronous event notification in a data storage system. Lower level software, such as a device driver or other software application generating events, reports the occurrence of an event to an event handler. The event handler implements... | 11/25/2008 |
| 7457910 | Method and system for managing partitions in a storage device A mass storage memory system and a method for re-allocating memory partition space is provided. The storage system includes a memory controller with a microprocessor that is adapted to receive data via a logical interface from a host system; a first memory partition... | 11/25/2008 |
| 7457918 | Grouping and group operations Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in and a storage plug-in. The eviction policy plug-in includes code to evict an object that is cached in the regi... | 11/25/2008 |
| 7457926 | Cache line replacement monitoring and profiling Systems and methods for cache replacement monitoring (CRM) are provided. The system includes a monitored cache comprising a monitored cache line set, the monitored cache line set comprising at least one cache line capable of holding data of a monitored address; and ... | 11/25/2008 |
| 7454573 | Cost-conscious pre-emptive cache line displacement and relocation mechanisms A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of r... | 11/18/2008 |
| 7454575 | Cache memory and its controlling method The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry ... | 11/18/2008 |
| 7454576 | System and method for cache coherency in a cache with different cache location lengths A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions ... | 11/18/2008 |
| 7454570 | Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved applicati... | 11/18/2008 |
| 7454565 | System and method for distributed partitioned library mapping Embodiments of the present invention provide a system and method of media library access that eliminates, or at least substantially reduces, the shortcomings of prior art media library access systems and methods. More particularly, embodiments of the present inventi... | 11/18/2008 |
| 7454589 | Data buffer circuit, interface circuit and control method therefor There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchron... | 11/18/2008 |
| 7454583 | Storage controller and control method for dynamically accomodating increases and decreases in difference data In a storage controller which stores data provided from a host system, creates a snapshot, which is a data image of a production volume at a given point in time, at regular or irregular intervals, and holds difference data of the snapshot in a pool volume, multiple ... | 11/18/2008 |
| 7454574 | Pre-fetch control method A pre-fetch control method comprises the following steps. First, after a data request for M-bytes request data sent from a cache controller is received, a determination is made on whether the M-bytes request data are found in the pre-fetch buffer. Then, a further de... | 11/18/2008 |
| 7451287 | Storage system and remote copy method for storage system A storage system including a primary storage device having a primary volume, and a secondary storage device having a secondary volume, a generation restoration portion, and a generation management volume. The secondary volume receives differential information from t... | 11/11/2008 |
| 7451279 | Storage system comprising a shared memory to access exclusively managed data A storage system includes a storage device, a shared memory, and first and second file server devices that each exclusively manages a respective portion of data stored on the storage device. During operation, the first file server device determines whether the first... | 11/11/2008 |
| 7451278 | Global pointers for scalable parallel applications Mapping of cacheable memory pages from other processes in a parallel job provides a very efficient mechanism for inter-process communication. A trivial address computation can then be used to look up a virtual address that allows the use of cacheable loads and store... | 11/11/2008 |
| 7451275 | Programming models for storage plug-ins Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in and a storage plug-in. The eviction policy plug-in includes code to evict an object that is cached in the regi... | 11/11/2008 |
| 7451269 | Ordering real-time accesses to a storage medium A method and system for servicing read requests directed to a storage medium by reordering the read requests when advantageous to do so and when the read requests can be serviced in a time-sensitive manner is provided. A reorder system determines whether it would be... | 11/11/2008 |
| 7451266 | Nonvolatile memory wear leveling by data replacement processing A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to... | 11/11/2008 |
| 7451263 | Shared interface for components in an embedded system Embodiments of the invention provide a method and apparatus for accessing a non-volatile memory controller and a volatile memory via a shared interface. In one embodiment, the method includes selecting one of the non-volatile memory controller and the volatile memor... | 11/11/2008 |
| 7447868 | Using vector processors to accelerate cache lookups Typical embodiments of the present invention maintain the cache metadata in arrays, and use vector instructions to process the array elements in parallel. The cache metadata comprises virtual tags corresponding to main memory addresses and physical addresses corresp... | 11/04/2008 |
| 7447867 | Non-intrusive address mapping having a modified address space identifier and circuitry therefor A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one exter... | 11/04/2008 |
| 7447860 | System and method for managing data associated with copying and recovery procedures in a data storage environment This invention is a system and method related to restoring data in a data storage environment and includes program logic. ... | 11/04/2008 |
| 7447850 | Associating events with the state of a data set In a data storage system, events are associated with the state of a data set at specific points in time, the data set being a collection of addressable storage that is modified by a host computer system writing to specific addresses, by capturing copies of writes ma... | 11/04/2008 |
| 7447831 | Memory systems for automated computing machinery Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller ... | 11/04/2008 |
| 7447830 | Information processing system and memory controller for controlling operation of memories An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories, and a memory controller controlling data transfer between the data pro... | 11/04/2008 |
| 7444468 | Storage system and method using interface control devices of different types A storage has NAS and SAN functions and a high degree of freedom to configure a system to reduce the management and operation cost. The storage includes a plurality of interface slots in which a plurality of interface controllers can be installed, a block I/O interf... | 10/28/2008 |
| 7444466 | Implementing feedback directed deferral of nonessential DASD operations A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a bu... | 10/28/2008 |
